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ADSP-2186L Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-2186L Datasheet(HTML) 2 Page - Analog Devices |
2 / 36 page ADSP-2186L –2– REV. B The ADSP-2186L’s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. In one processor cycle the ADSP-2186L can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation This takes place while the processor continues to: • Receive and transmit data through the two serial ports • Receive and/or transmit data through the internal DMA port • Receive and/or transmit data through the byte DMA port • Decrement timer Development System The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, sup- ports the ADSP-2186L. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction- level simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation’s GNU C Compiler, generates ADSP-2186L assembly source code. The source code debugger allows programs to be cor- rected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the ADSP-218x family: an ADSP- 218x-based evaluation board with PC monitor software plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low-cost, easy-to-use hard- ware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • 75 MHz ADSP-2189M • Full 16-bit Stereo Audio I/O with AD73322 Codec • RS-232 Interface • EZ-ICE Connector for Emulator Control • DSP Demo Programs • Evaluation Suite of Visual DSP The ADSP-218x EZ-ICE Emulator aids in the hardware debug- ging of an ADSP-2186L system. The emulator consists of hard- ware, host computer resident software, and the target board connector. The ADSP-2186L integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2186L device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including: • In-target operation • Up to 20 breakpoints • Single-step or full-speed operation • Registers and memory values can be examined and altered • PC upload and download functions • Instruction-level emulation of program booting and execution • Complete assembly and disassembly of instructions • C source-level debugging See Designing An EZ-ICE-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as well as the Target Board Connector for EZ-ICE Probe section of this data sheet, for the exact specifications of the EZ-ICE target board connector. Additional Information This data sheet provides a general overview of ADSP-2186L functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference. For more information about the develop- ment tools, refer to the ADSP-2100 Family Development Tools Data Sheet. ARCHITECTURE OVERVIEW The ADSP-2186L instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single pro- cessor cycle. The ADSP-2186L assembly language uses an alge- braic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. TIMER DATA ADDRESS GENERATORS DAG 2 DAG 1 SERIAL PORTS SPORT 1 SPORT 0 8K 16 DATA MEMORY 8K 24 PROGRAM MEMORY DATA MEMORY DATA DATA MEMORY ADDRESS PROGRAMMABLE I/O AND FLAGS BYTE DMA CONTROLLER MEMORY ADSP-2100 BASE ARCHITECTURE SHIFTER MAC ALU ARITHMETIC UNITS POWER-DOWN CONTROL PROGRAM SEQUENCER PROGRAM MEMORY ADDRESS PROGRAM MEMORY DATA EXTERNAL DATA BUS EXTERNAL ADDRESS BUS INTERNAL DMA PORT EXTERNAL DATA BUS OR FULL MEMORY MODE HOST MODE Figure 1. Block Diagram Figure 1 is an overall block diagram of the ADSP-2186L. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provi- sions to support multiprecision computations. The ALU per- forms a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arith- metic shifts, normalization, denormalization and derive expo- nent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. The internal result (R) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc. |
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