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ADSP-2171KS-104 Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-2171KS-104 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 52 page  ADSP-2171/ADSP-2172/ADSP-2173 REV. A –3– Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and pro- gram memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four pos- sible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses. • Program Memory Address (PMA) Bus • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus • Data Memory Data (DMD) Bus • Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Program memory can store both instructions and data, permit- ting the ADSP-217x to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP- 217x can fetch an operand from on-chip program memory and the next instruction in the same cycle. The memory interface supports slow memories and memory- mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR and BG). One execution mode (Go Mode) allows the ADSP-217x to continue running from inter- nal memory. Normal execution mode requires the processor to halt while buses are granted. In addition to the address and data bus for external memory connection, the ADSP-217x has a configurable 8- or 16-bit Host Interface Port (HIP) for easy connection to a host proces- sor. The HIP is made up of 16 data/address pins and 11 control pins. The HIP is extremely flexible and provides a simple inter- face to a variety of host processors. For example, the Motorola 68000 series, the Intel 80C51 series and the Analog Devices’ ADSP-2101 can be easily connected to the HIP. The host pro- cessor can initialize the ASDP-217x’s on-chip memory through the HIP. The ADSP-217x can respond to eleven interrupts. There can be up to three external interrupts, configured as edge or level sensi- tive, and eight internal interrupts generated by the Timer, the Serial Ports (“SPORTs”), the HIP, the powerdown circuitry, and software. There is also a master RESET signal. The two serial ports provide a complete synchronous serial in- terface with optional companding in hardware and a wide vari- ety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. Boot circuitry provides for loading on-chip program memory automatically from byte-wide external memory. After reset, seven wait states are automatically generated. This allows, for example, a 30 ns ADSP-217x to use an external 200 ns EPROM as boot memory. Multiple programs can be selected and loaded from the EPROM with no additional hardware. The on-chip program memory can also be initialized through the HIP. The ADSP-217x features three general-purpose flag outputs whose states can be simultaneously changed through software. You can use these outputs to signal an event to an external device. In addition, the data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n pro- cessor cycles, where n-l is a scaling value stored in an 8-bit regis- ter (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). The ADSP-217x instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single pro- cessor cycle. The ADSP-217x assembly language uses an alge- braic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Serial Ports The ADSP-217x incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-217x SPORTs. Refer to the ADSP-2100 Family User’s Manual for further details. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • SPORTs can use an external serial clock or generate their own serial clock internally. • SPORTs have independent framing for the receive and trans- mit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulse widths and timings. • SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law companding according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. • SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream. • SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration. |
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