ADSP-2163 datasheet(6/39 Pages) AD

Part #	ADSP-2163

Description	DSP Microcomputers with ROM

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REV. 0

ADSP-216x

–6–

CLKIN

CLKOUT

XTAL

ADSP-216x

Figure 2. External Crystal Connections

A clock output signal (CLKOUT) is generated by the processor,

synchronized to the processor’s internal cycles.

Reset

The

RESET signal initiates a complete reset of the ADSP-216x.

The

RESET signal must be asserted when the chip is powered

up to assure proper initialization. If the

RESET signal is applied

during initial power-up, it must be held long enough to allow

the processor’s internal clock to stabilize. If

RESET is activated

at any time after power-up and the input clock frequency does

not change, the processor’s internal clock continues and does

not require this stabilization time.

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid VDD is

applied to the processor and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 tCK cycles will ensure that the PLL has locked (this does

not, however, include the crystal oscillator start-up time).

During this power-up sequence the

RESET signal should be

held low. On any subsequent resets, the

RESET signal must

meet the minimum pulsewidth specification, tRSP.

To generate the

RESET signal, use either an RC circuit with an

external Schmidt trigger or a commercially available reset IC.

(Do not use only an RC circuit.)

The

RESET input resets all internal stack pointers to the empty

stack condition, masks all interrupts, and clears the MSTAT

register. When

RESET is released, the boot loading sequence is

performed (provided there is no pending bus request and the chip

is configured for booting, with MMAP = 0). The first instruction is

then fetched from internal program memory location 0x0000.

PIN FUNCTION DESCRIPTIONS

# of

Input/

Name(s)

Pins

Output

Function

Address

14

O

Address outputs for program, data and boot memory.

Data1

24

I/O

Data I/O pins for program and data memories. Input only for

boot memory, with two MSBs used for boot memory addresses.

Unused data lines may be left floating.

RESET

1

I

Processor Reset Input

IRQ2

1

I

External Interrupt Request #2

BR2

1

I

External Bus Request Input

BG

1

O

External Bus Grant Output

PMS

1

O

External Program Memory Select

DMS

1

O

External Data Memory Select

BMS

1

O

Boot Memory Select

RD

1

O

External Memory Read Enable

WR

1

O

External Memory Write Enable

MMAP

1

I

Memory Map Select Input

CLKIN, XTAL

2

I

External Clock or Quartz Crystal Input

CLKOUT

1

O

Processor Clock Output

VDD

Power Supply Pins

GND

Ground Pins

SPORT0

5

I/O

Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)

SPORT1

5

I/O

Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)

or Interrupts and Flags:

IRQ0 (RFS1)

1

I

External Interrupt Request #0

IRQ1 (TFS1)

1

I

External Interrupt Request #1

FI (DR1)

1

I

Flag Input Pin

FO (DT1)

1

O

Flag Output Pin

PWDACK3

1

O

Indicates when the processor has entered power-down.

PWDFLAG3

1

I

Low-to-High Transition of the Power-Down Flag. Input pin can

be used to terminate power-down.

NOTES

1Unused data bus lines may be left floating.

2

BR must be tied high (to V

DD) if not used.

3Only on ADSP-2165/ADSP-2166.

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