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CPC7220W Datasheet(PDF) 10 Page - IXYS Corporation |
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CPC7220W Datasheet(HTML) 10 Page - IXYS Corporation |
10 / 14 page PRELIMINARY INTEGRATED CIRCUITS DIVISION CPC7220 10 PRELIMINARY R00L 2.1 Truth Table Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the rising edge of the CLK signal. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF |
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Similar Description - CPC7220W |
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