REV. B

–8–

ADP3415

THEORY OF OPERATION

The ADP3415 is a dual MOSFET driver optimized for driving

two N-channel FETs in a synchronous buck converter topology.

A single duty ratio modulation signal is all that is required to

command the proper drive signal for the high-side and the

low-side FETs.

A more detailed description of the ADP3415 and its features

follows. Refer to the Functional Block Diagram (Figure 2).

Drive State Input

The drive state input, IN, should be connected to the duty ratio

modulation signal of a switch-mode controller. IN can be driven

by 2.5 V to 5.0 V logic. The FETs will be driven so that the SW

node follows the polarity of IN.

Low-Side Driver

The supply rails for the low-side driver, DRVL, are VCC and

GND. In its conventional application, it drives the gate of the

synchronous rectifier FET.

When the driver is enabled, the driver’s output is 180

° out of

phase with the duty ratio input aside from overlap protection

circuit, propagation, and transition delays. When the driver is

shut down or the entire ADP3415 is in shutdown or in under-

voltage lockout, the low-side gate is held low.

High-Side Driver

The supply rail for the high-side driver, DRVH, is between the

BST and SW pins and is created by an external bootstrap sup-

ply circuit. In its conventional application, it drives the gate of

the (top) main buck converter FET.

the SW pin is at ground, so the bootstrap capacitor will charge

up to VCC through DBST. As the supply voltage ramps up and

exceeds the UVLO threshold, the driver is enabled. When the

input pin, IN, goes high, the high-side driver will begin to turn

the gate of the FET. As Q1 turns ON, the SW pin will rise up to

gate to source voltage to hold Q1 ON. To complete the cycle,

when IN goes low, Q1 is switched OFF as DRVH discharges

the gate to the voltage at the SW pin. When the low-side FET,

Q2, turns ON, the SW pin is held at ground. This allows the

bootstrap capacitor to charge up to VCC again.

The high-side driver’s output is in phase with the duty ratio

input. When the driver is in undervoltage lockout, the high-side

gate is held low.

Overlap Protection Circuit

The overlap protection circuit (OPC) prevents both of the main

power switches, Q1 and Q2, from being ON at the same time.

This prevents excessive shoot-through currents from flowing

through both power switches and minimizes the associated

losses that can occur during their ON-OFF transitions. The

overlap protection circuit accomplishes this by adaptively

controlling the delay from Q1’s turn OFF to Q2’s turn ON and

by programming the delay from Q2’s turn OFF to Q1’s turn ON.

To prevent the overlap of the gate drives during Q1’s turn OFF

and Q2’s turn ON, the overlap circuit monitors the voltage at

the SW pin. When IN goes low, Q1 will begin to turn OFF

(after a propagation delay), but before Q2 can turn ON, the

overlap protection circuit waits for the voltage at the SW pin to

fallen to 1.6 V, Q2 will begin to turn ON. By waiting for the

voltage on the SW pin to reach 1.6 V, the overlap protection

circuit ensures that Q1 is OFF before Q2 turns on, regardless of

variations in temperature, supply voltage, gate charge, and drive

current. There is, however, a timeout circuit that will override

the waiting period for the SW pin to reach 1.6 V. After the

timeout period has expired, DRVL will be asserted regardless of

the SW voltage.

To prevent the overlap of the gate drives during Q2’s turn OFF

and Q1’s turn ON, the overlap circuit provides a programmable

delay that is set by a resistor on the DLY pin. When IN goes

high, Q2 will begin to turn OFF (after a propagation delay), but

before Q1 can turn ON, the overlap protection circuit waits for

the voltage at DRVL to go low. Once the voltage at DRVL is

low, the overlap protection circuit initiates a delay timer that is

adds an additional specified delay. The delay allows time for

current to commutate from the body diode of Q2 to an external

Schottky diode, which allows turn-off losses to be reduced.

Although not as foolproof as the adaptive delay, the program-

mable delay adds a safety margin to account for variations in size,

gate charge, and internal delay of the external power MOSFETs.

Low-Side Driver Shutdown

The low-side driver shutdown,

DRVLSD, allows a control

signal to shut down the synchronous rectifier. This signal should

be modulated by system state logic to achieve maximum battery

life under light load conditions and maximum efficiency under

heavy load conditions. Under heavy load conditions,

DRVLSD

should be high so that the synchronous switch is modulated for

maximum efficiency. Under light load conditions,

DRVLSD

should be low to prevent needless switching losses due to charge

shuttling caused by polarity reversal of the inductor current

when the average current is low.

When the

DRVLSD input is low, the low-side driver stays low.

When the

DRVLSD input is high, the low-side driver is enabled

and controlled by the driver signals as previously described.

Low-Side Driver Timeout Circuit

In normal operation, the DRVH signal tracks the IN signal

and turns OFF the Q1 high-side switch with a few tens of ns

When Q1 is turned OFF, then DRVL is allowed to go high,

Q2 to turn ON, and the SW node voltage to collapse to zero.

But in a faulty scenario, such as the case of a high-side Q1

switch drain-source short circuit when even DRVH goes low,

the SW node cannot fall to zero.

The ADP3415 has a timer circuit to address this scenario. Every

time the IN goes low, a DRVL on-time delay timer gets trig-

gered (see Figure 2). Should the SW node voltage not trigger

the low side turn-on, the DRVL on-time delay circuit will do it

high-side Q1 is still turned ON, i.e., its drain is shorted to the

source, the low-side Q2 turn-on will create a direct short circuit

the load (CPU) from potential damage that the high-side switch

short circuit could have caused.