MJW16010A

7

Motorola Bipolar Power Transistor Device Data

t, TIME (ms)

1

0.01

0.01

0.7

0.2

0.1

0.05

0.02

0.05

1

2

5

10

20

50

100

200

500

R

θJC(t) = r(t) RθJC

R

θJC = 1 or 0.92°CW

TJ(pk) – TC = P(pk) R

θJC(t)

P(pk)

t1

t2

DUTY CYCLE, D = t1/t2

D = 0.5

0.2

0.03

0.02

SINGLE PULSE

0.1

0.1

0.5

0.2

1000

Figure 18. Thermal Response

0.5

0.3

0.07

0.03

0.03

0.3

3

30

300

0.02

SAFE OPERATING AREA INFORMATION

FORWARD BIAS

There are two limitations on the power handling ability of a

transistor: average junction temperature and second break-

down. Safe operating area curves indicate IC – VCE limits of

the transistor that must be observed for reliable operation;

i.e., the transistor must not be subjected to greater dissipa-

tion than the curves indicate.

The data of Figures 14a and 14b is based on TC = 25_C;

TJ(pk) is variable depending on power level. Second break-

down pulse limits are valid for duty cycles to 10% but must be

derated when TC ≥ 25_C. Second breakdown limitations do

not derate the same as thermal limitations. Allowable current

at the voltages shown on Figures 14a and 14b may be found

at any case temperature by using the appropriate curve on

Figure 16.

TJ(pk) may be calculated from the data in Figure 18. At high

case temperatures, thermal limitations will reduce the power

that can be handled to values less than the limitations im-

posed by second breakdown.

REVERSE BIAS

For inductive loads, high voltage and high current must be

sustained simultaneously during turn–off, in most cases, with

the base–to–emitter junction reverse biased. Under these

conditions the collector voltage must be held to a safe level

at or below a specific value of collector current. This can be

accomplished by several means such as active clamping,

RC snubbing, load line shaping, etc. The safe level for these

devices is specified as Reverse Biased Safe Operating Area

and represents the voltage–current condition allowable dur-

ing reverse biased turn–off. This rating is verified under

clamped conditions so that the device is never subjected to

an avalanche mode. Figure 15 gives the RBSOA character-

istics.

SWITCHMODE DESIGN CONSIDERATIONS

1. FBSOA —

Allowable dc power dissipation in bipolar power transistors

decreases dramatically with increasing collector–emitter

voltage. A transistor which safely dissipates 100 watts at

10 volts will typically dissipate less than 10 watts at its rated

VCEO(sus). From a power handling point of view, current and

voltage are not interchangeable (see Application Note

AN875).

2. TURN–ON —

Safe turn–on load line excursions are bounded by pulsed

FBSOA curves. The 10

µs curve applies for resistive loads,

most capacitive loads, and inductive loads that are clamped

by standard or fast recovery rectifiers. Similarly, the 100 ns

curve applies to inductive loads which are clamped by ultra–

fast recovery rectifiers, and are valid for turn–on crossover

times less than 100 ns (see Application Note AN952).

At voltages above 75% of VCEO(sus), it is essential to pro-

vide the transistor with an adequate amount of base drive

VERY RAPIDLY at turn–on. More specifically, safe operation

according to the curves is dependent upon base current rise

time being less than collector current rise time. As a general

rule, a base drive compliance voltage in excess of 10 volts is

required to meet this condition (see Application Note

AN875).

3. TURN–OFF —

A bipolar transistor’s ability to withstand turn–off stress is

dependent upon its forward base drive. Gross overdrive vio-

lates the RBSOA curve and risks transistor failure. For this

reason, circuits which use fixed base drive are often more

likely to fail at light loads due to heavy overdrive (see Ap-

plication Note AN875).

4. OPERATION ABOVE VCEO(sus) —

When bipolars are operated above collector–emitter

breakdown, base drive is crucial. A rapid application of ade-

quate forward base current is needed for safe turn–on, as is

a stiff negative bias needed for safe turn–off. Any hiccup in

the base–drive circuitry that even momentarily violates either

of these conditions will likely cause the transistor to fail.

Therefore, it is important to design the driver so that its out-

put is negative in the absence of anything but a clean crisp

input signal (see Application Note AN952).