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AT45DB081D Datasheet(PDF) 11 Page - Analog Devices |
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AT45DB081D Datasheet(HTML) 11 Page - Analog Devices |
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11 / 53 page  11 3596O–DFLASH–1/2013 AT45DB081D The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. Table 7-3. Chip Erase Command Figure 7-1. Chip Erase Note: Refer to errata regarding Chip Erase on page 52. 7.8 Main Memory Page Program Through Buffer This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then programmed into a specified page in the main memory. To perform a main memory page program through buffer for the DataFlash standard page size (264-bytes), a 1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three address bytes. The address bytes are comprised of three don’t care bits, 12 page address bits, (PA11 - PA0) that select the page in the main memory where data is to be written, and nine buffer address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. To perform a main memory page program through buffer for the binary page size (256-bytes), the opcode 82H for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address bytes consisting of four don’t care bits, 12 page address bits (A19 - A8) that specify the page in the main memory to be written, and eight buffer address bits (BFA7 - BFA0) that selects the first byte in the buffer to be written. After all address bytes are clocked in, the part will take data from the input pins and store it in the specified data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transi- tion on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both the erase and the program- ming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the status register will indicate that the part is busy. 8. Sector Protection Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. The software controlled method relies on the use of software commands to enable and disable sector protection while the hardware con- trolled method employs the use of the Write Protect (WP) pin. The selection of which sectors that are to be protected or unprotected against program and erase operations is specified in the nonvolatile Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register. Command Byte 1 Byte 2 Byte 3 Byte 4 Chip Erase C7H 94H 80H 9AH Opcode Byte 1 Opcode Byte 2 Opcode Byte 3 Opcode Byte 4 CS Each transition represents 8 bits SI |
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Similar Description - AT45DB081D_13 |
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