Electronic Components Datasheet Search |
|
ADM805MARN Datasheet(PDF) 6 Page - Analog Devices |
|
ADM805MARN Datasheet(HTML) 6 Page - Analog Devices |
6 / 8 page ADM690A/ADM692A/ADM802L/M/ADM805L/M –6– REV. 0 Table I. Input and Output Status in Battery Backup Mode Signal Status VOUT VOUT is connected to VBATT via an internal PMOS switch. RESET Logic low. RESET Logic high (ADM805L, ADM805M). The open circuit output voltage is equal to VOUT. PFI The power fail comparator is disabled PFO Logic low. WDI The watchdog timer is disabled Power Fail Comparator The power fail comparator is an independent comparator that may be used to monitor the input power supply. The comparator’s inverting input is internally connected to a 1.25 V reference voltage. The noninverting input is available at the PFI input. This input may be used to monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output (PFO) goes low indicating a power failure. For early warning of power failure the comparator may be used to monitor the preregulator input simply by choosing an appropriate resistive divider network. The PFO output can be used to interrupt the processor so that a shutdown procedure is implemented before the power is lost. 1.25V POWER FAIL OUTPUT (PFO) POWER FAIL INPUT INPUT POWER R1 R2 Figure 9. Power Fail Comparator Adding Hysteresis to the Power Fail Comparator For increased noise immunity, hysteresis may be added to the power fail comparator. Since the comparator circuit is non- inverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 10. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, resistor R3 sources current into the PFI summing junction. This results in differing trip levels for the comparator. Further noise immunity may be achieved by connecting a capacitor between PFI and GND. 1.25V (PFO) INPUT POWER R1 R2 PFI R3 TO µP NMI 5V PFO 0V 0V VL VH VIN VH = 1.25 1+ R1 R2+R3 R2 × R3 VL = 1.25+R1 1.25 VCC–1.25 R2 R3 VMID= 1.25 R1+R2 R2 – Figure 10. Adding Hysteresis to the Power Fail Comparator TYPICAL APPLICATIONS Figure 11 shows a typical power monitoring, battery backup application. VOUT powers the CMOS RAM. Under normal operating conditions with VCC present, VOUT is internally connected to VCC. If a power failure occurs, VCC will decay and VOUT will be switched to VBATT thereby maintaining power for the CMOS RAM. A RESET pulse is also generated when VCC falls below the reset threshold. CMOS RAM POWER µP RESET µP NMI I/O LINE µP SYSTEM VCC µP POWER VOUT RESET PFO WDI GND VBATT PFI UNREGULATED DC R1 R2 +5V BATTERY + Figure 11. Typical Application Circuit The watchdog timer input (WDI) monitors an I/O line from the µP system. This line must be toggled once every 1.6 seconds to verify correct software execution. Failure to toggle the line indicates that the µP system is not correctly executing its program and may be tied up in an endless loop. If this happens, a reset pulse is generated to initialize the processor. |
Similar Part No. - ADM805MARN |
|
Similar Description - ADM805MARN |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |