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AOZ1031AI Datasheet(PDF) 10 Page - Alpha & Omega Semiconductors |
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AOZ1031AI Datasheet(HTML) 10 Page - Alpha & Omega Semiconductors |
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10 / 15 page  AOZ1031AI Rev. 1.6 March 2010 www.aosmd.com Page 10 of 15 In a buck converter, output capacitor current is continu- ous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calcu- lated by: Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and induc- tor ripple current is high, output capacitor could be over- stressed. Loop Compensation The AOZ1031A employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole can be calculated by: The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor. The compensation design is actually to shape the con- verter control loop transfer function to get desired gain and phase. Several different types of compensation net- work can be used for the AOZ1031A. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1031A, FB pin and COMP pin are the inverting input and the output of internal error amplifier. A series R and C compensation network connected to COMP pro- vides one pole and one zero. The pole is: where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the error amplifier voltage gain, which is 500 V/V, and C2 is compensation capacitor in Figure 1. The zero given by the external compensation network, capacitor C2 and resistor R3, is located at: To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover is the also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concern. When design- ing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. The AOZ1031A operates at a frequency range from 500kHz to 700kHz. It is recommended to choose a crossover fre- quency equal or less than 40kHz. The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calcu- late RC: where; fC is desired crossover frequency. For best performance, fC is set to be about 1/10 of switching frequency, VFB is 0.8V, GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, and GCS is the current sense circuit transconductance, which is 6.68 A/V. The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fP1 but lower than 1/5 of selected cross- over frequency. CC can is selected by: I CO_RMS ΔI L 12 ---------- = f P1 1 2 π C O R L × × ----------------------------------- = f Z1 1 2 π C O ESR CO × × ------------------------------------------------ = f P2 G EA 2 π C C G VEA × × ------------------------------------------- = f Z2 1 2 π C C R C × × ----------------------------------- = f C 40kHz = R C f C V O V FB ---------- 2 π C 2 × G EA G CS × ------------------------------ × × = C C 1.5 2 π R C f P1 × × ----------------------------------- = |
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