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ADM706AN Datasheet(PDF) 3 Page - Analog Devices |
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ADM706AN Datasheet(HTML) 3 Page - Analog Devices |
3 / 8 page ADM705–ADM708 REV. B –3– PIN FUNCTION DESCRIPTION Pin No. ADM705 ADM707 ADM706 ADM708 Mnemonic DIP, SOIC DIP, SPOC MicroSOIC Function MR 1 1 3 Manual Reset Input. When taken below 0.8 V, a RESET is gener- ated. MR can be driven from TTL, CMOS logic or from a manual reset switch as it is internally debounced. An internal 250 µA pull-up current holds the input high when floating. VCC 2 2 4 5 V Power Supply Input. GND 3 3 5 0 V. Ground reference for all signals. PFI 4 4 6 Power-Fail Input. PFI is the noninverting input to the Power-Fail Comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected to GND or VCC. PFO 5 5 7 Power-Fail Output. PFO is the output from the Power-Fail Compara- tor. It goes low when PFI is less than 1.25 V. WDI 6 N/A N/A Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period, the watch- dog output WDO goes low. The timer resets with each transition at the WDI input. Either a high-to-low or a low-to-high transition will clear the counter. The internal timer is also cleared whenever reset is asserted. The watchdog timer is disabled when WDI is left floating or connected to a three-state buffer. NC N/A 6 8 No Connect. RESET 7 7 1 Logic Output. RESET goes low for 200 ms when triggered. It can be triggered either by VCC being below the reset threshold or by a low signal on the manual reset ( MR) input. RESET will remain low whenever VCC is below the reset threshold (4.65 V in ADM705, 4.4 V in ADM706). It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout will not trigger RESET unless WDO is connected to MR. WDO 8 N/A N/A Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog timer times out as a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as V CC goes above the reset threshold, WDO goes high immediately. RESET N/A 8 2 Logic Output. RESET is an active high output suitable for systems that use active high RESET logic. It is the inverse of RESET. PIN CONFIGURATION DIP, SOIC DIP, SOIC MicroSOIC 1 2 3 4 8 7 6 5 TOP VIEW (Not to Scale) NC = NO CONNECT ADM707/ ADM708 RESET GND PFI PFO NC RESET MR VCC 8 7 6 5 1 2 3 4 TOP VIEW (Not to Scale) ADM705/ ADM706 MR PFO WDI RESET WDO VCC GND PFI 8 7 6 5 1 2 3 4 TOP VIEW (Not to Scale) NC = NO CONNECT ADM707/ ADM708 MR PFO NC RESET RESET VCC GND PFI |
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