REV. B

ADC912A

–6–

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Description

l

AIN

Analog Input. 0 V to 10 V.

2

VREFIN

Voltage Reference Input. Requires external –5 V reference.

3

AGND

Analog Ground.

4...11

Three-state data outputs become active when

CS and RD are brought low.

13 . ..16

Individual pin function is dependent upon High Byte Enable (HBEN) input.

DATA BUS OUTPUT,

CS and RD = LOW

Pin 4

Pin 5

Pin 6

Pin 7

Pin 8

Pin 9

Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16

Mnemonic

*

HBEN = LOW

HBEN = HIGH

Low

Low

Low

Low

1

2

DGND

Digital Ground.

17

CLK IN

Clock Input Pin. An external TTL-compatible clock may be applied to this pin. Alternatively a crystal or

ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18).

18

CLK OUT

Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is used. See

CLK IN (Pin 17) description for crystal (resonator).

19

HBEN

High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto the lower

conversion start when HBEN is high.

20

RD

READ Input. This active LOW signal, in conjunction with

CS, is used to enable the output data three

state drivers and initiates a conversion if CS and HBEN are low.

21

CS

Chip Select Input. This active LOW signal, in conjunction with

RD, is used to enable the output data

three-state drivers and initiates a conversion if

RD and HBEN are low.

22

BUSY

BUSY output indicates converter status. BUSY is LOW during conversion.

23

Negative Supply, –12 V or –15 V.

24

Positive Supply, +5 V.

PIN CONFIGURATION

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

HBEN

CLK OUT

CLK IN

BUSY

CS

RD

AGND

DGND

ADC912A

TOP VIEW

(Not to Scale)

1

2

3

4

5

6

7

8

9

10

11

12

AGND

DGND

C1

+

0V TO 10V

ANALOG INPUT

–5V

REFERENCE

SOURCE

ADC912A

8-BIT OR 16-BIT

P DATA BUS

XTAL = 1MHz, C1 = 0.1

F, C3 = 10

F

C3, C4 = 30pF TO 100pF DEPENDING ON XTAL CHOSEN

24

23

22

21

20

19

18

17

16

15

14

13

+5V

–12V TO –15V

STATUS

OUTPUT

P

CONTROL

INPUTS

XTAL

C3

C4

HBEN

CLK OUT

CLK IN

BUSY

CS

RD

C2

Figure 10. Basic Connection Diagram