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ISL94203IRTZ-T Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL94203IRTZ-T Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 64 page ISL94203 3 FN7626.2 December 5, 2012 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1, 3, 5, 7, 9, 11, 13, 15, 17 VC8, VC7, VC6, VC5, VC4, VC3, VC2, VC1, VC0 Battery cell n voltage input. This pin is used to monitor the voltage of this battery cell. The voltage is level shifted to a ground reference and is monitored internally by an ADC converter. VCn connects to the positive terminal of a battery cell (CELLN) and VC(n-1)the negative terminal of CELLN (VSS connects with the negative terminal of CELL1). 2, 4, 6, 8, 10, 12, 14, 16 CB8, CB7, CB6, CB5, CB4, CB3, CB2, CB1 Cell balancing FET control output n. This internal drive circuit controls an external FET used to divert a portion of the current around a cell while the cell is being charged or adds to the current pulled from a cell during discharge in order to perform a cell voltage balancing operation. This function is generally used to reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned on or off by an internal cell balance state machine or an external controller. 18, 28, 29 VSS Ground. This pin connects to the most negative terminal in the battery string. 19 VREF Voltage Reference Output. This output provides a 1.8V reference voltage for the internal circuitry and for the external microcontroller. 20, 21 XT1, XT2 Temperature monitor inputs. These pins input the voltage across two external thermistors used to determine the temperature of the cells and or the power FET. When this input drops below the threshold, an external over-temperature condition exists. 22 TEMPO Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. The thermistor is located in close proximity to the cells or the power FET. The TEMPO output is connected internally to the VREF voltage through a PMOS switch only during a measurement of the temperature, otherwise the TEMPO output is off. 23, 30 DNC Do Not Connect 24 ADDR Serial Address. This is an address input for an I2C communication link to allow for two cascaded devices on one bus. 25 SCL Serial Clock. This is the clock input for an I2C communication link. 26, 27 SDAI, SDAO Serial Data. These are the data lines for an I2C interface. When connected together they form the standard bi-directional interface for the I2C bus. When separated, they can use separate level shifters for a cascaded operation. 31 INT Interrupt. This pin goes active low, when there is an external µC connected to the ISL94203 and µC communication fails to send a slave byte within a watchdog timer period. This is a CMOS type output. 32 PSD Pack Shutdown. This pin goes active high, when any cell voltage reaches the OVLO threshold (OVLO flag). Optionally, PSD is also set if there is a voltage differential between any two cells that is greater than a specified limit (CELLF flag), or if there is an open wire condition. This pin can be used for blowing a fuse in the pack or as an interrupt to an external µC. 33 FETSOFF FETSOFF. This input allows an external microcontroller to turn off both Power FET and CB outputs. 34 SD Shutdown. This output indicates that the ISL94203 detected any failure condition that would result in the DFET turning off. This could be undervoltage, overcurrent, over- or under-temperature, etc. The SD pin also goes active if there is any charge overcurrent condition. This is an open drain output. 35 EOC End-of-Charge. This output indicates that the ISL94203 detected a fully charged condition. This is defined by any cell voltage exceeding an EOC voltage (as defined by an EOC value in EEPROM). 36 RGO Regulator Output. This is the 2.5V regulator output. 37 CHMON Charge Monitor. This input monitors the charger connection. When the IC is in the sleep mode, connecting this pin to the charger wakes up the device. When the IC recovers from a charge overcurrent condition, this pin is used to monitor that the charger is removed prior to turning on the power FETs. In a single path configuration, this pin and the LDMON pin connect together. 38 LDMON Load Monitor. This pin monitors the load connection. When the IC is in the sleep mode, connecting this pin to a load wakes up the device. When the IC recovers from a discharge overcurrent or short circuit condition, this pin is used to monitor that the load is removed prior to turning on the power FETs. In a single path configuration, this pin and the CHMON pin connect together. 39, 40, 41 C3, C2, C1 Charge Pump Capacitor Pins. These external capacitors are used for the charge pump driving the power FETs. |
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