ESMT

M12L2561616A (2K)

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2012

Revision: 1.4

5/45

° )

Parameter

Value

Unit

Input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall-time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

-5

-6

-7

Unit

Note

Row active to row active delay

10

12

14

ns

1

RAS to CAS delay

15

18

20

ns

1

Row precharge time

15

18

20

ns

1

40

42

45

ns

1

Row active time

100

us

@ Operating

55

60

63

ns

1

Row cycle time

@ Auto refresh

55

60

70

ns

1,5

Last data in to col. address delay

1

CLK

2

Last data in to row precharge

10

12

14

ns

1,2

Last data in to burst stop

1

CLK

2

Refresh period (8,192 rows)

64

ms

6

Col. address to col. address delay

1

CLK

3

CAS latency = 3

2

Number of valid

Output data

CAS latency = 2

1

ea

4

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is

8x7.8 μ s.)