AD9831

–6–

REV. A

±2 MHz about the fundamental frequency. The narrow band

SFDR gives the attenuation of the largest spur or harmonic in a

bandwidth of

±50 kHz about the fundamental frequency.

Clock Feedthrough

There will be feedthrough from the MCLK input to the analog

output. Clock feedthrough refers to the magnitude of the

MCLK signal relative to the fundamental frequency in the

AD9831’s output spectrum.

Table I. Control Registers

Register

Size

Description

FREQ0 REG

32 Bits

Frequency Register 0. This de-

fines the output frequency, when

FSELECT = 0, as a fraction of the

MCLK frequency.

FREQ1 REG

32 Bits

Frequency Register 1. This de-

fines the output frequency, when

FSELECT = 1, as a fraction of the

MCLK frequency.

PHASE0 REG

12 Bits

Phase Offset Register 0. When

PSEL0 = PSEL1 = 0, the contents

of this register are added to the

output of the phase accumulator.

PHASE1 REG

12 Bits

Phase Offset Register 1. When

PSEL0 = 1 and PSEL1 = 0, the con-

tents of this register are added to

the output of the phase accumulator.

PHASE2 REG

12 Bits

Phase Offset Register 2. When

PSEL0 = 0 and PSEL1 = 1, the con-

tents of this register are added to

the output of the phase accumulator.

PHASE3 REG

12 Bits

Phase Offset Register 3. When

PSEL0 = PSEL1 = 1, the contents

of this register are added to the

output of the phase accumulator.

Table II. Addressing the Control Registers

A2

A1

A0

Destination Register

0

0

0

FREQ0 REG 16 LSBs

0

0

1

FREQ0 REG 16 MSBs

0

1

0

FREQ1 REG 16 LSBs

0

1

1

FREQ1 REG 16 MSBs

1

0

0

PHASE0 REG

1

0

1

PHASE1 REG

1

1

0

PHASE2 REG

1

1

1

PHASE3 REG

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The

endpoints of the transfer function are zero scale, a point 0.5

LSB below the first code transition (000 . . . 00 to 000 . . . 01)

and full scale, a point 0.5 LSB above the last code transition

(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.

Differential Nonlinearity

This is the difference between the measured and ideal 1 LSB

change between two adjacent codes in the DAC.

Signal to (Noise + Distortion)

Signal to (Noise + Distortion) is measured signal to noise at the

output of the DAC. The signal is the rms magnitude of the

fundamental. Noise is the rms sum of all the nonfundamental

ing the dc component. Signal to (Noise + Distortion) is

dependent on the number of quantization levels used in the

digitization process; the more levels, the smaller the quantiza-

tion noise. The theoretical Signal to (Noise + Distortion) ratio

for a sine wave input is given by

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

where N is the number of bits. Thus, for an ideal 10-bit con-

verter, Signal to (Noise + Distortion) = 61.96 dB.

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the rms sum

of harmonics to the rms value of the fundamental. For the

AD9831, THD is defined as

THD

= 20 log

3

4

5

6

2

sixth harmonic.

Output Compliance

The output compliance refers to the maximum voltage which

can be generated at the output of the DAC to meet the specifi-

cations. When voltages greater than that specified for the

output compliance are generated, the AD9831 may not meet

the specifications listed in the data sheet.

Spurious Free Dynamic Range

Along with the frequency of interest, harmonics of the funda-

mental frequency and images of the MCLK frequency are

present at the output of a DDS device. The spurious free dy-

namic range (SFDR) refers to the largest spur or harmonic

which is present in the band of interest. The wide band SFDR

gives the magnitude of the largest harmonic or spur relative to

the magnitude of the fundamental frequency in the bandwidth

Table III. Frequency Register Bits

D15

D0

MSB

LSB

Table IV. Phase Register Bits

D15

D14

D13

D12

D11

D0

XXXX

MSB

LSB