M12L64164A-5TG2M datasheet(2/45 Pages) ESMT

Part #	M12L64164A-5TG2M

Description	1M x 16 Bit x 4 Banks

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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ESMT

M12L64164A (2M)

Elite Semiconductor Memory Technology Inc.

Publication Date: Apr. 2012

Revision: 1.6

2/45

FUNCTIONAL BLOCK DIAGRAM

PIN FUNCTION DESCRIPTION

NAME

INPUT FUNCTION

CLK

System Clock

Active on the positive going edge to sample all inputs

CS

Chip Select

Disables or enables device operation by masking or enabling all

inputs except CLK , CKE and L(U)DQM

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior new command.

Disable input buffers for power down in standby.

A0 ~ A11

Address

Row / column address are multiplexed on the same pins.

Row address : RA0~RA11, column address : CA0~CA7

BA1 , BA0

Bank Select Address

Selects bank to be activated during row address latch time.

Selects bank for read / write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with

RAS low.

Enables row access & precharge.

CAS

Column Address Strobe

Latches column address on the positive going edge of the CLK with

CAS low.

Enables column access.

WE

Write Enable

Enables write operation and row precharge.

Latches data in starting from CAS , WE active.

L(U)DQM

Data Input / Output Mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0 ~ DQ15

Data Input / Output

Data inputs / outputs are multiplexed on the same pins.

VDD / VSS

Power Supply / Ground

Power and ground for the input buffers and the core logic.

VDDQ / VSSQ

Data Output Power / Ground

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

NC

No Connection

This pin is recommended to be left No Connection on the device.

L(U)DQM

DQ

Mode

Register

Column

Address

Buffer

&

Refresh

Counter

Row

Address

Buffer

&

Refresh

Counter

Bank D

Bank A

Bank B

Bank C

Sense Amplifier

Column Decoder

Data Control Circuit

Address

Clock

Generator

CLK

CKE

CS

RAS

CAS

WE

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