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AD9803 Datasheet(PDF) 3 Page - Analog Devices |
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AD9803 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 19 page  –3– REV. 0 AD9803 CCD-MODE SPECIFICATIONS Parameter Min Typ Max Units POWER CONSUMPTION VDD = 2.7 150 mW VDD = 2.8 170 mW VDD = 3.0 185 mW MAXIMUM CLOCK RATE 18 MHz CDS Gain 0dB Allowable CCD Reset Transient 1 500 mV Max Input Range Before Saturation 1 1000 mV p-p PGA Max Input Range 1000 mV p-p Max Output Range 1000 mV p-p Digital Gain Control (See Figure 26) Gain Control Resolution 10 (Fixed) Bits Minimum Gain (Code 0) –3.5 –1.5 0 dB Low Gain (Code 207) 0 4 8 dB Medium Gain (Code 437) 15 dB High Gain (Code 688) 22 26 30 dB Max Gain (Code 1023) 32 dB Analog Gain Control (See Figure 25) PGACONT1 = 0.7 V, PGACONT2 = 1.5 V 4.5 dB PGACONT1 = 1.8 V, PGACONT2 = 1.5 V 26 dB BLACK-LEVEL CLAMP Clamp Level (Selected by the Serial I/F) CLP(0) (E-Reg 00) 34 LSB CLP(1) (E-Reg 01) 50 LSB CLP(2) (E-Reg 10) 66 LSB CLP(3) (E-Reg 11) 18 LSB Even-Odd Offset 2 ±0.5 LSB SIGNAL-TO-NOISE RATIO 3 (@ Minimum PGA Gain) 61 dB TIMING SPECIFICATIONS 4 Pipeline Delay Even-Odd Offset Correction Disabled 5 Cycles Even-Odd Offset Correction Enabled 7 Cycles Internal Clock Delay 5 (t ID)3 ns Inhibited Clock Period (tINHIBIT)15 ns Output Delay (tOD) 20 ns Output Hold Time (tHOLD)2 ns ADCCLK, SHP, SHD, Clock Period 47 55.6 ns ADCCLK Hi-Level, Or Low Level 20 28 ns SHP, SHD Minimum Pulsewidth 6 10 14 ns SHP Rising Edge to SHD Rising Edge 20 28 ns NOTES 1Input Signal Characteristics defined as shown: 50mV MAX OPTICAL BLACK PIXEL 500mV TYP RESET TRANSIENT 1V MAX INPUT SIGNAL RANGE 2V MAX INPUT SIGNAL W/PBLK ENABLED 2Even-Odd Offset is described under the Theory of Operation section. The Even-Odd Offset is measured with the Even-Off Offset correction enabled. 3SNR = 20 log 10 (Full-Scale Voltage/RMS Output Noise). 420 pF loading; timing shown in Figure 1. 5Internal aperture delay for actual sampling edge. 6Active Low Clock Pulse Mode (C-Reg 00). Specifications subject to change without notice. (TMIN to TMAX, ACVDD = ADVDD = DVDD = +2.8 V, fSHP = fSHD = fADCCLK = 18 MHz unless otherwise noted) |
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Similar Description - AD9803 |
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