1

PRELIMINARY TECHNICAL DATA

a

12-Bit, 160 MSPS

2

×××××/4×××××/8××××× Interpolating

AD9773

FEATURES

12 bit Resolution, 160 MSPS Conversion Rate

Selectable 2

×/4×/8× Interpolating Filter

Programmable Channel Gain and Offset Adjustment

Fs/2,4,8 Digital Quadrature Modulation Capability

Direct IF Transmission Mode for 70MHz+ IFs

Enables Image Rejection Architecture

Fully Compatible SPI Port

Excellent AC Performance

- SFDR -69dBc @ 2-35MHz

-WCDMA ACPR -70dB @ IF=16.25 MHz

Internal PLL Clock Multiplier

Selectable Internal Clock Divider

Versatile Clock Input

-Differential/Single Ended

-Sine Wave or TTL/CMOS/LVPECL Compatible

Versatile Input Data Interface

-2’s Complement/Straight Binary Data Coding

-Dual Port or Single Port Interleaved Data

Single +3.3V Supply Operation

Power Dissipation: <700 mW @ 3.3V

On-chip 1.2 V Reference, 80-Lead LQFP

APPLICATIONS

Communications:

Analog Quadrature Modulation Architectures

3G, Multi-Carrier GSM, TDMA, CDMA Systems

Multi-Level QAM Modulators, Instrumentation

PRODUCT DESCRIPTION

The AD9773 is the 12 bit member of the AD977x family of

pin-compatible, high performance, programmable 2

×/4×/8×

interpolating TxDAC+s. The AD977x family features a serial

port interface (SPI) providing a high level of programmabil-

ity thus allowing for enhanced system level options. These

options include: selectable 2

×/4×/8× interpolation filters;

Fs/2, Fs/4 or Fs/8 digital quadrature modulation with image

rejection; a direct IF mode; programmable channel gain

and offset control; programmable internal clock divider;

straight binary or two’s complement data interface; and a

single port or dual port data interface.

BLOCK DIAGRAM

REV. PrA

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

Q DAC

I DAC

PHASE DETEC-

TOR & VCO

PRESCALER

DIFF.

REFCLK

COS

SIN

COS

SIN

HALF- B AND

FILTER#3*

DATA

ASSEMB LER

HALF- B AND

FILTER #1*

HALF- B AND

FILTER #2*

22

(FDAC)

12

22

12

Q

LATCH

I

LATCH

MUX

CONTROL

12

12

FILTER

B YP ASS MUX

P ROGRAMAB LE DUAL INTERP OLATION DAC

WITH IMAGE REJECTION/DIGITAL MODULATION

WRITE

SELECT

22

22

22

22

+

-/+

+

+/-

CLOCK OUT

*Half- B and Filter s also can be configur ed for " Zer o- Stuffing Only"

SP I INTERFACE &

CONTROL REGISTERS

I DAC

P LL CLOCK MULTIP LIER

AND CLOCK DIVIDER

2

2

2

2