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EDJ2108EDBG-GN-F Datasheet(PDF) 1 Page - Elpida Memory |
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EDJ2108EDBG-GN-F Datasheet(HTML) 1 Page - Elpida Memory |
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1 / 150 page  Document No. E1797E41 (Ver. 4.1) Date Published February 2012 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2011-2012 DATA SHEET 2G bits DDR3L SDRAM EDJ2104EDBG (512M words × 4 bits) EDJ2108EDBG (256M words × 8 bits) Specifications • Density: 2G bits • Organization 64M words × 4 bits × 8 banks (EDJ2104EDBG) 32M words × 8 bits × 8 banks (EDJ2108EDBG) • Package 78-ball FBGA Lead-free (RoHS compliant) and Halogen-free • Power supply: 1.35V (typ.) VDD, VDDQ = 1.283V to 1.45V Backward compatible for VDD, VDDQ = 1.5V ± 0.075V • Data rate 1600Mbps/1333Mbps/1066Mbps (max.) • 1KB page size Row address: A0 to A14 Column address: A0 to A9, A11 (EDJ2104EDBG) A0 to A9 (EDJ2108EDBG) • Eight internal banks for concurrent operation • Burst lengths (BL): 8 and 4 with Burst Chop (BC) • Burst type (BT): Sequential (8, 4 with BC) Interleave (8, 4 with BC) • /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11 • /CAS Write Latency (CWL): 5, 6, 7, 8 • Precharge: auto precharge option for each burst access • Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω) • Refresh: auto-refresh, self-refresh • Refresh cycles Average refresh period 7.8 µs at 0°C ≤ TC ≤ +85°C 3.9 µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C Features • Double-data-rate architecture: two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; center- aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • On-Die Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT • Multi Purpose Register (MPR) for pre-defined pattern read out • ZQ calibration for DQ drive and ODT • Programmable Partial Array Self-Refresh (PASR) • /RESET pin for Power-up sequence and reset function • SRT range: Normal/extended • Programmable Output driver impedance control |
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