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AD9742AR Datasheet(PDF) 11 Page - Analog Devices |
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AD9742AR Datasheet(HTML) 11 Page - Analog Devices |
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11 / 20 page  REV. 0 AD9742 –11– IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of –1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9742. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.2 V for an IOUTFS = 20 mA to 1.0 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differ- ential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. DIGITAL INPUTS The AD9742’s digital section consists of 12 input bit channels and a clock input. The 12-bit parallel data inputs follow stan- dard positive binary coding where DB11 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. DVDD DIGITAL INPUT Figure 6. Equivalent Digital Input The digital interface is implemented using an edge-triggered master/ slave latch. The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as 165 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. DAC TIMING Input Clock and Data Timing Relationship Dynamic performance in a DAC is dependent on the relation- ship between the position of the clock edges and the point in time at which the input data changes. The AD9742 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9742 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 7 shows the relationship of SFDR to clock placement with different sample rates. Note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. –3 –2 2 –1 0 1 70 80 TIME (ns) OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE 3 60 50 40 65 75 55 45 fOUT = 50MHz fOUT = 20MHz Figure 7. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz Sleep Mode Operation The AD9742 has a power-down function that turns off the output current and reduces the supply current to less than 4 mA over the specified supply range of 3.0 V to 3.6 V and tempera- ture range. This mode can be activated by applying a logic level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 ¥ AVDD. This digital input also contains an active pull- down circuit that ensures the AD9742 remains enabled if this input is left disconnected. The AD9742 takes less than 50 ns to power down and approximately 5 ms to power back up. POWER DISSIPATION The power dissipation, PD, of the AD9742 is dependent on several factors that include: • The power supply voltages (AVDD and DVDD) • The full-scale current output I OUTFS • The update rate f CLOCK • The reconstructed digital input waveform The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS as shown in Figure 8 and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figure 9 shows IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V. |
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