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AD9708-EB Datasheet(PDF) 7 Page - Analog Devices |
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AD9708-EB Datasheet(HTML) 7 Page - Analog Devices |
7 / 16 page AD9708 –7– REV. B FUNCTIONAL DESCRIPTION Figure 12 shows a simplified block diagram of the AD9708. The AD9708 consists of a large PMOS current source array capable of providing up to 20 mA of total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The remaining 3 LSBs are also implemented with equally weighted current sources whose sum total equals 7/8th of an MSB current source. Implementing the upper and lower bits with current sources helps maintain the DAC’s high output impedance (i.e. > 100 k Ω). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. The analog and digital sections of the AD9708 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 volt to 5.5 volt range. The digital section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier. The full-scale output current is regulated by the reference con- trol amplifier and can be set from 2 mA to 20 mA via an exter- nal resistor, RSET. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is mirrored over to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is thirty-two times the value of IREF. DAC TRANSFER FUNCTION The AD9708 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 255), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB are a function of both the input code and IOUTFS and can be expressed as: IOUTA = (DAC CODE/256) × I OUTFS (1) IOUTB = (255 – DAC CODE)/256 × I OUTFS (2) where DAC CODE = 0 to 255 (i.e., Decimal Representation). As previously mentioned, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO and external resistor RSET. It can be expressed as: IOUTFS = 32 × I REF (3) where IREF = VREFIO/RSET (4) The two current outputs will typically drive a resistive load directly. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, which are tied to analog common, ACOM. Note, RLOAD may repre- sent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply: VOUTA = IOUTA × R LOAD (5) VOUTB = IOUTB × R LOAD (6) Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The differential voltage, VDIFF, appearing across IOUTA and IOUTB is: VDIFF = (IOUTA – IOUTB) × R LOAD (7) Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be expressed as: VDIFF = {(2 DAC CODE – 255)/256}/ × (32 R LOAD/RSET) × V REFIO (8) VOLTAGE REFERENCE AND CONTROL AMPLIFIER The AD9708 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external refer- ence. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM, as shown in Figure 13, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 µF or greater from REFIO to REFLO. Note that REFIO is not designed to drive any ex- ternal load. It should be buffered with an external amplifier having an input bias current less than 100 nA if any additional loading is required. +1.20V REF REFLO REFIO FS ADJ 50pF COMP1 0.1 F CURRENT SOURCE ARRAY +5V AVDD SEGMENTED SWITCHES LATCHES DVDD DCOM CLOCK SLEEP IOUTA IOUTB COMP2 ACOM 0.1 F +5V RSET 2k 0.1 F AD9708 IOUTB VOUTB RLOAD 50 VOUTA RLOAD 50 IOUTA VDIFF = VOUTA – VOUTB CLOCK IREF VREFIO DIGITAL DATA INPUTS (DB7–DB0) Figure 12. Functional Block Diagram |
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