AD9561

–5–

REV. 0

Pulse Pattern Example

Figure 1 at the top of the previous page illustrates the PWM

OUT of the AD9561 with various DATA and CONTROL

inputs. The DATA format is Binary. In the Pulse Pattern

decimal 255.

The top line shows the CLOCK; the second shows DATA and

CONTROL inputs, which are latched on the rising edge of

CLOCK. The third line shows the resulting pulse.

The AD9561 DATA and CONTROL inputs are double

latched. The OUTPUT pulse labeled “Pulse N” results from

DATA and CONTROL values latched in by the first CLOCK,

illustrating the one CLOCK period timing delay.

The CONTROL value number for pulse one is shown as xx.

This means the value is not important because a 100% pulse

will be output for any CONTROL value for DATA value 255 or

not care), also noting that CONTROL value is unimportant.

The fourth DATA/CONTROL value is C0/0X. This indicates

that the level for LEM/TEM is unimportant when SEM/DEM is

logic Level “0”.

Because the AD9561 must provide full range coverage of the

CLOCK pulse period, the ramp time must be matched to the

CLOCK period. All components for the ramp generators, except

CLOCK period. The ramps are generated by constant current

sources charging on-chip capacitors.

operation to 16.5 k

Ω for 1 MHz. Because the absolute value of

the on-chip capacitor can vary by

±20%, the autocalibration

circuit is included to fine tune the matching of the ramp time to

the CLOCK period.

100

10

1

020

1

10

frequency range. The following equation should be used to

R

=

30.2068

where F is the CLOCK frequency in Hz. The resistor value

determined by the equation will generate a current near center-

range of the autocalibration circuit.

Autocalibration

The AD9561 should be calibrated when power is applied to the

system or after a power reduce cycle.

CAL START

CAL OUT

1µs MIN

Figure 4. Autocalibration Timing

Autocalibration is initiated by applying a pulse of 1

µs minimum

duration to Pin 17, CAL START. The CLOCK pulse should be

applied continuously during calibration. As Figure 4 shows, the

initial state of CAL OUT is not known.

During the CAL IN pulse, all internal logic is initialized for

calibration and proper synchronization once calibration is

complete; the falling edge of CAL IN initiates the Auto-CAL

cycle.

Auto-CAL is not affected by the code applied to the DATA or

CONTROL inputs. However, to assure that no pulses are

generated during calibration, it is suggested that all digital

inputs be held at Logic “0.”

On the falling edge of CAL IN, the ramp’s slope is set as slow as

increasing as autocalibration adds small incremental currents,

until it crosses the internal REF LO before the end of the

CLOCK period.

RAMP

REF LO

RAMP

END OF CLOCK CYCLE

TIME

Figure 5. Autocalibration Conceptual

The calibration current is incremented on each 32nd CLOCK

pulse until the full-scale ramp time is equal to the period of the

CLOCK. Cal Complete is detected and CAL OUT goes high

when the ramp crosses REF LO before it is reset by the next

CLOCK. With a maximum of 64 incremental increases, the

equation:

32

× 64

where: