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MSC8126 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MSC8126 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 48 page  MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15 Freescale Semiconductor 2 Table of Contents 1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .7 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2 Recommended Operating Conditions. . . . . . . . . . . . . .14 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14 2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .15 2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .40 3.1 Start-up Sequencing Recommendations . . . . . . . . . . .40 3.2 Power Supply Design Considerations. . . . . . . . . . . . . .40 3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .42 3.4 External SDRAM Selection . . . . . . . . . . . . . . . . . . . . . .43 3.5 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . .44 4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 List of Figures Figure 1. MSC8126 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. StarCore SC140 DSP Extended Core Block Diagram . . 3 Figure 3. MSC8126 Package, Top View . . . . . . . . . . . . . . . . . . . . 5 Figure 4. MSC8126 Package, Bottom View . . . . . . . . . . . . . . . . . . 6 Figure 5. Overshoot/Undershoot Voltage for VIH and VIL. . . . . . . 16 Figure 6. Start-Up Sequence: VDD and VDDH Raised Together . . 17 Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN . . . . . 18 Figure 9. Timing Diagram for a Reset Configuration Write . . . . . . 21 Figure 10.Internal Tick Spacing for Memory Controller Signals. . . 22 Figure 11.SIU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12.CLKOUT and CLKIN Signals. . . . . . . . . . . . . . . . . . . . . 26 Figure 13.DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 14.Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 15.Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 16.Asynchronous Broadcast Write Timing Diagram . . . . . . 30 Figure 17.DSI Synchronous Mode Signals Timing Diagram . . . . . 31 Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 21.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 22.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 23.MDIO Timing Relationship to MDC . . . . . . . . . . . . . . . . 34 Figure 24.MII Mode Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 26.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 27.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 28.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 29.Test Clock Input Timing Diagram. . . . . . . . . . . . . . . . . . 38 Figure 30.Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . . . 38 Figure 31.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . 39 Figure 32.TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 33.Core Power Supply Decoupling. . . . . . . . . . . . . . . . . . . 41 Figure 34.VCCSYN Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 35.MSC8126 Mechanical Information, 431-pin FC-PBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 |
Similar Part No. - MSC8126_V15 |
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Similar Description - MSC8126_V15 |
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