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NR3012T2R2M Datasheet(PDF) 2 Page - Panasonic Semiconductor |
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NR3012T2R2M Datasheet(HTML) 2 Page - Panasonic Semiconductor |
2 / 27 page AN30181A 2 Ver. BEB ABSOLUTE MAXIMUM RATINGS *1 *3 V – 0.3 to (VIN + 0.3) LX1,LX2,PCNT,PCNTB,DIS, RESET,BUF,VREG Output Voltage Range *1 *3 V – 0.3 to (VIN + 0.3) EN,FB1,FB2 Input Voltage Range - kV 2 HBM (Human Body Model) *2 °C – 40 to + 150 Tj Operating junction temperature ESD *2 °C – 55 to + 150 Tstg Storage temperature Notes Unit Rating Symbol Parameter *2 °C – 40 to + 85 Topr Operating free-air temperature *1 *3 V 6.0 VIN Supply voltage Notes) Do not apply external currents and voltages to any pin not specifically mentioned. This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1:The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2:Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25 °C. *3:V IN is voltage for AVIN, PVIN1 = PVIN2,(VIN + 0.3) V must not be exceeded 6 V. POWER DISSIPATION RATING *1 Notes 0.765 W 1.472 W 84.9 °C /W 9pin Wafer level chip size package (WLCSP Type) PD(Ta=85 °C) PD(Ta=25 °C) θ JA PACKAGE Note). For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. *1:Glass Epoxy Substrate(4 Layers) [Glass-Epoxy: 50 X 50 X 0.8t(mm)] Die Pad Exposed , Soldered. CAUTION Although this has limited built-in ESD protection circuit, but permanent damage may occur on it. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates |
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