MMA8450Q

Sensors

8

Freescale Semiconductor, Inc.

2.3

1. All values referred to VIH (min) and VIL (max) levels.

Parameter

Symbol

Unit

Min

Max

SCL Clock Frequency

Pullup = 1 k

Pullup = 1 k

0

0

400

TBD

kHz

kHz

Bus Free Time between STOP and START Condition

1.3

μs

Repeated START Hold Time

0.6

μs

Repeated START Setup Time

0.6

μs

STOP Condition Setup Time

0.6

μs

3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(4)

stretches the SCL, the data must be valid by the setup time before it releases the clock.

μs

μs

μs

SDA Setup Time

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the

specification) before the SCL line is released. Also the acknowledge timing must meet this setup time

Ns

SCL Clock Low Time

4.7

μs

SCL Clock High Time

4

μs

SDA and SCL Rise Time

1000

Ns

8. Cb = total capacitance of one bus line in pF.

This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding

10.In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for

this when considering bus timing

300

Ns

Pulse width of spikes on SDA and SCL that must be suppressed by input filter

50

Ns