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AD8348 Datasheet(PDF) 7 Page - Analog Devices |
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AD8348 Datasheet(HTML) 7 Page - Analog Devices |
7 / 13 page PRELIMINARY TECHNICAL DATA Rev. PrF 2/11/03 - 7 - Theory of operation VGA The VGA is implemented using the patented X-AMP architecture. The single-ended IF signal is attenuated in eight discrete 6-dB steps by a passive R-2R ladder. Each discrete attenuated version of the IF signal is applied to the input of a transconductance stage. The current outputs of all transconductance stages are summed together and drive a resistive load at the output of the VGA. Gain control is achieved by smoothly turning on and off the relevant transconductance stages with a temperature-compenstated interpolation circuit. This scheme allows the gain to continuously varied over a 48dB range with linear-in-dB gain control. This configuration also keeps the relative dynamic range constant (e.g. IIP3-NF in dB) over gain setting. The absolute intermodulation intercepts and noise figure, however, vary directly with gain. The analog voltage VGIN sets the gain. VGIN=0V is the maximum gain setting, and VGIN=1.2V is the minimum voltage gain setting. Downconversion mixers The output of the VGA drives two (I & Q) double-balanced Gilbert-cell down-conversion mixers. Alternatively, the VGA can be disabled by driving the ENVG pin low and the mixers can be driven directly externally via the MXIP, MXIN port. At the input of the mixer, a degenerated differential pair performs linear voltage-to-current conversion. The differential output current feeds into the mixer core where it is downconverter by the mixing action of the Gilbert cell. The phase splitter provides quadrature LO signals which drive the LO ports of the in- phase and quadrature mixers. Buffers at the output of each mixer drive pins IMXO and QMXO respectively. These linear, low-output impedance buffers drive 40ohm temperature-stable, passive resistors in series with each of the output pins (IMXO, QMXO). This 40ohms should be considered when calculating the reverse termination if an external filter is inserted between IMXO(QMXO) and IAIN(QAIN). The DC output level of the buffer is set by the VCMO pin. This can be set externally or connected to the on-chip 1.0V reference VREF. Phase splitter Quadrature generation is achieved using a divide-by-two frequency divider. Unlike a poly-phase filter which achieves quadrature over a limited frequency range, the divide-by-two approach maintains quadrature over a broad frequency range and does not attenuate the LO. The user, however, must provide an external reference XLO which is twice the frequency of the desired LO frequency. XLO drives the clock inputs of two flip-flops which divide down the frequency by a factor of two. The outputs of the two flip-flops are one half- period of XLO out of phase. Equivalently, the outputs are one quarter-period (90 degrees) of the desired LO frequency out of phase. Because the transitions on XLO define the phase difference at the outputs, deviation from 50% duty cycle translates directly to quadrature phase errors. Baseband amplifiers Two (I &Q) fixed-gain (20dB), single-ended to differential amplifers are provided to amplify the demodulated signal after off-chip filtering. The amplifiers use voltage feedback to linearize the gain over the demolation bandwidth. These amplifiers can be used to maximize the dynamic range at the input of an ADC following the AD8348. The input to the baseband amplifiers IAIN (QAIN) feeds into the base of a bipolar transistor with an input impedance of roughly 100kohm. The baseband amplifiers sense the single- ended difference between IAIN (QAIN) and VCMO. IAIN can be DC biased by terminating with a shunt resistor to VCMO, such as when an external filter is inserted between IMXO (QMXO) and IAIN (QAIN). Alternatively, any DC connection to IMXO (QXMO) can provide appropriate bias via the offset-nulling loop. Bias The global bias for the chip is controlled by a master biasing cell that can be disabled using the ENBL pin. If the ENBL is held low, the entire chip will power down to a low-power sleep mode typically consuming 60uA at 5V. Baseband offset cancellation A low output current integrator senses the output voltage offset at IOPP,IOPN (QOPP,QOPN) and injects a nulling current into the signal path. The integration time constant of the offset nulling loop is set by capacitor COFS from IOFS (QOFS) to VCMO. This forms a high-pass response for the baseband signal path with a lower 3dB frequency of 1 2 200 pass OFS f C π = ⋅Ω⋅ Alternatively, the user can externally adjust the DC offset by driving IOFS (QOFS) with a digital-to-analog converter or other voltage source. In this case, the baseband circuit will operate all the way down to DC (fpass=0Hz). The integrator output current is only 50uA and can be easily overridden with an external voltage source. The IOFS (QOFS) pin must be either connected to a bypass capacitor (>0.1uF) or an external voltage source to prevent the feedback loop from oscillating. AD8348 |
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