REV. 0

AD8345

–11–

Note that this circuit assumes that the single-ended I and Q signals

are ground referenced. Any differential dc-offsets will result

in increased LO Leakage at the output of the AD8345.

It is possible to drive the baseband inputs with a single-ended

signal biased to 0.7 V, with the unused inputs being biased to a

dc level of 0.7 V. However, this mode of operation is not recom-

mended because any dc level difference between the bias level of

the drive signal and the dc level on the unused input (including

the effect of temperature drift) will result in increased LO

leakage. In addition, the maximum output power will be reduced

by 6 dB.

RF Output

The RF output is designed to drive a 50

Ω load but should be ac

coupled as shown in Figure 3. If the I and Q inputs are driven in

quadrature by 1.2 V p-p signals, the resulting output power will

be approximately –1 dBm (see TPC 1).

The RF output impedance is very close to 50

Ω. As a result, no

additional matching circuitry is required if the output is driving

a 50

Ω load.

Application with TxDAC

Figure 6 shows the AD8345 driven by the AD9761 TxDAC

(any of the devices in ADI’s TxDAC family can also be used in

this application). The signal from the DAC is being filtered by a

differential 51 MHz low-pass filter.

The I and Q DACs generate differential output currents of 0 mA

to 20 mA and 20 mA to 0 mA, respectively. When loaded with

50

Ω ground-referenced resistors, this would produce a 2 V p-p

differential signal (i.e., 1 V p-p on each output) with a common-

mode level of 0.5 V. In the configuration shown, each DAC output

sees a composite load of 48

Ω (10 Ω + 51 Ω (100 Ω + 51 Ω)) in

the passband. So, for example, when IOUTA is driven to its

positive full scale, IBBP will be equal to 0.96 V. With IOUTB

at 0 mA, the voltage at IBBN will be equal to 0.456 V. This

results in a full-scale differential signal of approximately 1 V p-p

which will have a common-mode level of 0.7 V.

Soldering Information

The AD8345 is packaged in a 16-lead TSSOP package with

exposed pad. For optimum thermal conductivity, the exposed

pad can be soldered to the exposed metal of a ground plane.

This results in a junction-to-air thermal impedance (

30

°C/W. However, soldering is not necessary for safe operation.

If exposed pad is not soldered down, the

Evaluation Board

Figure 7. Shows the schematic of the AD8345 evaluation board.

Note that uninstalled components are marked as open. This is a

4-layer board, with the two center layers used as ground plane

and top and bottom layers used as signal and power planes.

5.5 V. The power supply is decoupled by a 0.01

µF and 1000 pF

capacitors. The circuit closely follows the basic connection

schematic with SW1 in B Position. If SW1 is in Position A, the

Enable pin will be pulled to ground by a 10 k

Ω resistor and the

device will be in its power-down mode.

All connectors are SMA-type. The I and Q inputs are dc-coupled

to allow a direct connection to a dual DAC with differential

outputs. Resistor pads are provided in case termination at the

I and Q inputs is required. The local oscillator input (LO) is

terminated to approximately 50

Ω with an external 50 Ω resistor

to ground. A 1:1 wide-band transformer (ETC1-1-13) provides

a differential drive to the AD8345’s differential LO input. The

device can also be driven single-ended by shorting out T1.

33pF

100

310nH

33pF

310nH

51

10

51

33pF

100

310nH

33pF

310nH

51

10

51

PHASE

SPLITTER

VOUT

IBBP

IBBN

QBBP

QBBN

AD8345

LOIP

LOIN

VPS1

VPS2

IOUTB

IOUTA

“I”

DAC

2

LATCH

“I”

“Q”

DAC

2

LATCH

“Q”

QOUTA

0.1 F

2k

REFIO

FS ADJ

SLEEP

SELECT

WRITE

CLOCK

AD9761

MUX

CONTROL

AVDD

DVDD

DCOM

QOUTB

DAC

DATA

INPUTS

Figure 6. AD8345/TxDAC Interface