AD7721

REV. A

–11–

a linear phase response. This is very difficult to achieve with

analog filters.

Analog filters, however, can remove noise superimposed on the

signal before it reaches the ADC. Digital filtering cannot do this

and noise peaks riding on signals, near full-scale, have the po-

tential to overload the analog modulator even though the aver-

age value of the signal is within limits.

0.0

–50.0

–100.0

–150.0

FREQUENCY

Figure 9a. 128 Tap FIR Filter Frequency Response

0.0

–50.0

–100.0

–150.0

FREQUENCY

Figure 9b. 83 Tap FIR Filter Frequency Response

SERIAL INTERFACE

The AD7721’s serial communication port allows easy inter-

facing to industry-standard microprocessors, microcontrollers

and digital signal processors. The AD7721 is operated in self-

clocking mode, the AD7721 providing the serial clock. The

RFS signal is also provided by the AD7721 by tying RFS to

DRDY.

Figure 10 shows the timing diagram for reading from the

AD7721.

DRDY goes high to indicate that a conversion has

been completed.

DRDY remains high for one internal clock

(15 MHz) cycle and then goes low for the next 31 clock cycles.

New data is loaded into the output shift register on the rising

edge of

DRDY. When DRDY goes low, the data is accessed

from the AD7721. Although the AD7721 has a 12-bit digital

output in the parallel mode, sixteen bits of data are available for

transmission in the serial mode, starting with the MSB. Serial

data is clocked out of the device on the rising edge of SCLK

and is valid on the falling edge of SCLK.

CIRCUIT DESCRIPTION

Sigma-Delta ADC

The AD7721 ADC employs a sigma-delta conversion technique

that converts the analog input into a digital pulse train.

Due to the high oversampling rate, which spreads the quantiza-

in the band of interest is reduced (Figure 8a). To reduce the

quantization noise further, a high order modulator is employed

to shape the noise spectrum, so that most of the noise energy is

shifted out of the band of interest (Figure 8b).

The digital filter that follows the modulator removes the large

out of band quantization noise (Figure 8c), while converting the

digital pulse train into parallel 12 bit wide binary data or serial

16 bit wide binary data.

BAND OF

INTEREST

QUANTIZATION NOISE

a.

BAND OF

INTEREST

NOISE

SHAPING

b.

BAND OF

INTEREST

DIGITAL FILTER CUTOFF FREQUENCY

WHICH EQUALS 152.8kHz (10MHz) OR

229.2kHz (15MHz)

c.

Figure 8. Sigma-Delta ADC

Digital Filter

The digital filter that follows the modulator removes the large

out of band quantization noise, while converting the one bit

digital pulse train into 12-bit or 16-bit wide binary data. The

rate is a little over twice the signal bandwidth which guarantees

that there is no loss of data in the signal band.

The AD7721 employs 2 FIR filters in series. The first filter is a

The second filter is an 83 tap half-band filter that samples the

frequency response of the 2 filters is shown in Figure 9.

Digital filtering has certain advantages over analog filtering.

First, since digital filtering occurs after the A/D conversion, it

can remove noise injected during the conversion process. Ana-

log filtering cannot do this. Second, the digital filter combines

low passband ripple with a steep roll off, while also maintaining