REV. 0

AD7719

–7–

Parameter

(B Version)

Unit

Conditions/Comments

32.768

kHz typ

Crystal Oscillator Frequency.

50

ns min

RESET Pulsewidth

Read Operation

0

ns min

RDY to CS Setup Time

0

ns min

4

0

ns min

SCLK Active Edge to Data Valid Delay

3

60

ns max

80

ns max

4, 5

0

ns min

60

ns max

80

ns max

100

ns min

SCLK High Pulsewidth

100

ns min

SCLK Low Pulsewidth

0

ns min

6

10

ns min

Bus Relinquish Time after SCLK Inactive Edge

3

80

ns max

100

ns max

SCLK Active Edge to

Write Operation

0

ns min

30

ns min

Data Valid to SCLK Edge Setup Time

25

ns min

Data Valid to SCLK Edge Hold Time

100

ns min

SCLK High Pulsewidth

100

ns min

SCLK Low Pulsewidth

0

ns min

CS Rising Edge to SCLK Edge Hold Time

NOTES

CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.

lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the

part and as such are independent of external bus loading capacitances.

7

RDY returns high after a read of both ADCs. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur

close to the next output update.

1.6V

TO OUTPUT

PIN

50pF

Figure 1. Load Circuit for Timing Characterization

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE