REV. A

AD7716

–4–

Parameter

(B Version)

Units

Conditions/Comments

3, 4

400

kHz min

CLKIN Frequency

8

MHz max

5

40

ns max

Digital Output Rise Time. Typically 20 ns

5

40

ns max

Digital Output Fall Time. Typically 20 ns

ns min

CASCIN Pulse Width

ns min

CASCIN to DRDY Setup Time

ns max

DRDY

Low to SCLK Low Delay

50

ns max

CLKIN High to DRDY Low, SCLK Active, RFS Active

40

ns max

CLKIN High to SCLK High Delay

50

ns min

SCLK Width

ns

SCLK Period

40

ns max

SCLK High to RFS High Delay

ns

RFS

Pulse Width

6

45

ns max

SCLK High to SDATA Valid Delay

7

ns max

SCLK Low to SDATA High Impedance Delay

ns min

ns max

CLKIN High to DRDY High Delay

50

ns max

CLKIN High to RFS High Impedance, SCLK High Impedance

20

ns min

ns max

SCLK Low to CASCOUT High Delay

ns

CASCOUT Pulse Width

NOTES

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish

time of the part and as such is independent of external bus loading capacitances.

5%; AGND = DGND = 0 V;

Figure 3. Master Mode Timing Diagram

DB31

CH1

t

20

t

21

CASCIN (I)

SCLK (O)

RFS (O)

SDATA (O)

CASCOUT (O)

t

17

t

8

t

7

t

18

t

19

t

9

t

11

t

10

t

12

t

13

t

12

t

19

t

15

t

14

t

16

DB30

CH1

DB29

CH1

DB25

CH1

DB24

CH1

DB23

CH1

DB2

CH4

DB1

CH4

DB0

CH4

CLKIN (I)

DRDY (O)