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AD7707BR Datasheet(PDF) 7 Page - Analog Devices |
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AD7707BR Datasheet(HTML) 7 Page - Analog Devices |
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7 / 40 page  REV. A AD7707 –7– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in smaller batches of data. 2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock frequencies in the range 500 kHz to 5 MHz. 3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user does not require it, this MCLK OUT can be turned off via the CLK DIS bit of the Clock Register. This ensures that the part is not wasting unnecessary power driving capacitive loads on MCLK OUT. 4 CS Chip Select. Active low Logic Input used to select the AD7707. With this input hard-wired low, the AD7707 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7707. 5 RESET Logic Input. Active low input that resets the control logic, interface logic, calibration coeffi- cients, digital filter and analog modulator of the part to power-on status. 6AVDD Analog Supply Voltage, +2.7 V to +5.25 V operation. 7 AIN1 Low Level Analog Input Channel 1. This is used as a pseudo-differential input with respect to LOCOM. 8 LOCOM COMMON Input for low level input channels. Analog inputs on AIN1 and AIN2 must be refer- enced to this input. 9 AIN2 Low Level Analog Input Channel 2. This is used as a pseudo-differential input with respect to LOCOM. 10 AIN3 Single-Ended High Level Analog Input Channel with respect to HICOM. 11 HICOM COMMON Input for high level input channel. Analog input on AIN3 must be referenced to this input. 12 VBIAS VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and AIN(–) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected to 2.5 V when AVDD = 5 V and 1.225 V when AVDD = 3 V. 13 REF IN(+) Reference Input. Positive input of the differential reference input to the AD7707. The reference input is differential with the provision that REF IN(+) must be greater than REF IN(–). REF IN(+) can lie anywhere between AVDD and AGND. PIN CONFIGURATION TOP VIEW (Not to Scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD7707 AIN3 AIN2 LOCOM MCLK IN MCLK OUT CS AIN1 AVDD RESET HICOM VBIAS REF IN(+) DVDD DIN DOUT REF IN(–) AGND DRDY SCLK DGND |
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