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PCA9555A Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCA9555A Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 39 page PCA9555A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 11 September 2012 6 of 39 NXP Semiconductors PCA9555A Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up 6.2.2 Input port register pair (00h, 01h) The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. The default value ‘X’ is determined by the externally applied logic level. An Input port register read operation is performed as described in Section 7.2 “Reading the port registers”. 6.2.3 Output port register pair (02h, 03h) The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that was written to these registers, not the actual pin value. A register pair write is described in Section 7.1 and a register pair read is described in Section 7.2. Table 5. Input port 0 register (address 00h) Bit 7 6 5 4 3 2 1 0 Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0 Default XX XX XX XX Table 6. Input port 1 register (address 01h) Bit 7 6 5 4 3 2 1 0 Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0 Default XX XX XX XX Table 7. Output port 0 register (address 02h) Bit 7 6 5 4 3 2 1 0 Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0 Default 11 11 11 11 Table 8. Output port 1 register (address 03h) Bit 7 6 5 4 3 2 1 0 Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0 Default 11 11 11 11 |
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