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AD725 Datasheet(PDF) 17 Page - Analog Devices

Part No. AD725
Description  Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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 17 page
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AD725
REV. 0
–17–
6
3
–24
0.1
10.0
1.0
0
–3
–6
–9
–12
–15
–18
–21
FREQUENCY – MHz
LUMA PIN
COMP PIN
Figure 25. Luminance Frequency Response with NTSC Trap
SYNCHRONIZING SIGNALS
The AD725 requires explicit horizontal and vertical synchroniz-
ing signals for proper operation. This information cannot and
should not be incorporated in any of the RGB signals. However,
the synchronizing information can be provided as either separate
horizontal (HSYNC) and vertical (VSYNC) signals or as a
single composite sync (CSYNC) signal.
Internally the AD725 requires a composite sync logic signal that
is mostly high and goes low during horizontal sync time. The
vertical interval will have an inverted duty cycle from this. This
signal should occur at the output of an on-chip XNOR gate on
the AD725 whose two inputs are HSYNC (Pin 16) and VSYNC
(Pin 15). There are several options for meeting these conditions.
The first is to have separate signals for HSYNC and VSYNC.
Each should be mostly low and then high going during their
respective time of assertion. This is the convention used by
RGB monitors for most PCs. The proper composite sync signal
will be produced by the on-chip XNOR gate when using these
inputs.
If a composite sync signal is already available, it can be input
into HSYNC (Pin 16), while VSYNC (Pin 15) can be used to
change the polarity. (In actuality, HSYNC and VSYNC are
interchangeable since they are symmetric inputs to a two-input
gate).
If the composite sync input is mostly high and then low going
for active HSYNC time (and inverted duty cycle during VSYNC),
then it is already of the proper polarity. Pulling VSYNC high,
while inputting the composite sync signal to HSYNC will pass
this signal though the XNOR gate without inversion.
On the other hand, if the composite sync signal is the opposite
polarity as described above, pulling VSYNC low will cause the
XNOR gate to invert the signal. This will make it the proper
polarity for use inside the AD725. These logic conditions are
illustrated in Figure 26.
HSYNC
VSYNC
CSYNC
Figure 26. Sync Logic Levels (Equalization and Serration Pulses Not Shown)




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