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AD674BAD Datasheet(PDF) 3 Page - Analog Devices |
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AD674BAD Datasheet(HTML) 3 Page - Analog Devices |
3 / 12 page REV. C –3– CONVERTER START TIMING (Figure 1) J, K, A, B Grades T Grade Parameter Symbol Min Typ Max Min Typ Max Unit Conversion Time 8-Bit Cycle (AD674B) tC 68 10 68 10 µs 12-Bit Cycle (AD674B) tC 912 15 912 15 µs 8-Bit Cycle (AD774B) tC 45 6 45 6 µs 12-Bit Cycle (AD774B) tC 6 7.3 8 6 7.3 8 µs STS Delay from CE tDSC 200 225 ns CE Pulsewidth tHEC 50 50 ns CS to CE Setup tSSC 50 50 ns CS Low During CE High tHSC 50 50 ns R/ C to CE Setup tSRC 50 50 ns R/ C LOW During CE High tHRC 50 50 ns A0 to CE Setup tSAC 00 ns A0 Valid During CE High tHAC 50 50 ns READ TIMING—FULL CONTROL MODE (Figure 2) J, K, A, B Grades T Grade Parameter Symbol Min Typ Max Min Typ Max Unit Access Time CL = 100 pF tDD 1 75 150 75 150 ns Data Valid After CE Low tHD 25 2 25 2 ns 20 3 15 4 ns Output Float Delay tHL 5 150 150 ns CS to CE Setup tSSR 50 50 ns R/ C to CE Setup tSRR 00 ns A0 to CE Setup tSAR 50 50 ns CS Valid After CE Low tHSR 00 ns R/ C High After CE Low tHRR 00 ns A0 Valid After CE Low tHAR 50 50 ns NOTES 1t DD is measured with the load circuit of Figure 3a and is defined as the time required for an output to cross 0.4 V or 2.4 V. 20 °C to T MAX. 3At –40 °C. 4At –55 °C. 5t HL is defined as the time required for the data lines to change 0.5 V when loaded with the circuit of Figure 3b. Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at TMIN, 25 °C, and T MAX. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. Specifications subject to change without notice. Parameter Test Conditions Min Max Unit LOGIC INPUTS VIH High Level Input Voltage 2.0 VLOGIC + 0.5 V VIL Low Level Input Voltage –0.5 +0.8 V IIH High Level Input Current VIN = VLOGIC –10 +10 µA IIL Low Level Input Current VIN = 0 V –10 +10 µA CIN Input Capacitance 10 pF LOGIC OUTPUTS VOH High Level Output Voltage IOH = 0.5 mA 2.4 V VOL Low Level Output Voltage IOL = 1.6 mA 0.4 V IOZ High-Z Leakage Current VIN = 0 to VLOGIC –10 +10 µA COZ High-Z Output Capacitance 10 pF DIGITAL SPECIFICATIONS (For all grades TMIN to TMAX with VCC = +15 V 10% or +12 V 5%, VLOGIC = +5 V 10%, VEE = –15 V 10% or –12 V 5%, unless otherwise noted.) SWITCHING SPECIFICATIONS (For all grades TMIN to TMAX with VCC = +15 V 10% or +12 V 5%, VLOGIC = +5 V 10%, VEE = –15 V 10% or –12 V 5%, unless otherwise noted.) tHEC tHSC tSSC tHRC tSRC tSAC tHAC tC tDSC CE CS R/ C A0 STS DB11 – DB0 HIGH IMPEDANCE Figure 1. Convert Start Timing tSSR CE CS R/ C A0 STS DB11 – DB0 tHSR tHRR tHAR tHD tSAR tSRR HIGH IMPEDANCE DATA VALID HIGH IMPEDANCE tHL tDD Figure 2. Read Cycle Timing DBN 3k 100pF DBN 3k 100pF 5V HIGH-Z TO LOGIC 0 HIGH-Z TO LOGIC 1 High-Z to Logic 1 High-Z to Logic 0 Figure 3a. Load Circuit for Access Time Test DBN 3k 100pF LOGIC 1 TO HIGH-Z DBN 3k 100pF 5V LOGIC 0 TO HIGH-Z Logic 1 to High-Z Logic 0 to High-Z Figure 3b. Load Circuit for Output Float Delay Test AD674B/AD774B |
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