AD53509 datasheet(3/8 Pages) AD

Part #	AD53509

Description	High-Performance Driver/Comparator Active Load on a Single Chip

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–3–

REV. A

AD53509

Parameter

Min

Typ

Max

Unit

Test Conditions

Delay Change vs. Pulsewidth

50

ps

VL = 0 V, VH = 2 V, Pulsewidth = 2.5 ns/7.5 ns, 30 ns/90 ns

Minimum Pulsewidth

3 V Swing

1.4

ns

VL = 0 V, VH = 3 V, 90% (2.7 V) Reached, Measure @ 50%

5 V Swing

2.0

ns

VL = 0 V, VH = 5 V, 90% (4.5 V) Reached, Measure @ 50%

Toggle Rate

250

MHz

VL = 0 V, VH = 5 V, VDUT > 3.0 V p-p

DYNAMIC PERFORMANCE, INHIBIT

Delay Time, Active to Inhibit

3.3

ns

Measured at 50%, VH = +2 V, VL = –2 V, VT = 0 V

Delay Time, Inhibit to Active

2.9

ns

Measured at 50%, VH = +2 V, VL = –2 V, VT = 0 V

Delay Time Matching (Z)

<2

ns

Z = Delay Time Active to Inhibit Test (Above)—

Delay Time Inhibit to Active Test (Above)

(Of Worst Two Edges)

I/O Spike

150

mV, p-p

VH = 0 V, VL = 0 V, VT = 0 V

Rise, Fall Time, Active to Inhibit

1.6

ns

VH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)

Rise, Fall Time, Inhibit to Active

1.4

ns

VH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)

DYNAMIC PERFORMANCE , VTERM

Delay Time, VH to VTERM, VL to VTERM

2.5

ns

Measured at 50%, VL = –1 V, VH = +1 V, VTERM = 0 V

Delay Time, VTERM to VH and VTERM to VL

2.5

ns

Measured at 50%, VL = VH = +0.4 V, VTERM = –0.4 V

Overshoot and Preshoot

<3.0 + 75

% of Step + mV

VH/VL, VTERM = (0 V, –1 V), (0 V, –2.0 V),

(0 V, 6.0 V)

VTERM Mode Rise Time

2.2

ns

VL = –2 V, VH = +2 V, VTERM = 0 V, 20%–80%

VTERM Mode Fall Time

2.2

ns

VL = –2 V, VH = +2 V, VTERM = 0 V, 20%–80%

PSRR, DRIVE or TERM Mode

35

dB

VS = VS

± 3%

Specifications subject to change without notice.

COMPARATOR SPECIFICATIONS

(All specifications are at TJ = 85 C

5 C. [Outputs terminated in 150

to GND, +VS = 11 V

3% –VS = 6 V

3%, VCCO = 3.3 V unless

otherwise specified.] All temperatures coefficients are measured at TJ = 75 C to 95 C.)

Parameter

Min

Typ

Max

Unit

Test Conditions

DC INPUT CHARACTERISTICS

Offset Voltage (VOS)

–25

+25

mV

CMV = 0 V

Offset Voltage (Drift)

50

µV/°C

CMV = 0 V

HCOMP, LCOMP Bias Current

–50

+50

µAVIN = 0 V

Voltage Range (VCM)

–2

+7.0

V

Differential Voltage (VDIFF)

9.0

V

Gain and Linearity

–0.05

+0.05

% FSR

VIN = –2 V to +7 V (9 V FSR)

LATCH ENABLE INPUTS

Logic “1” Current (IIH)

250

µA

LEA,

LEA, LEB, LEB = +3 V

Logic “0” Current (IIL)

–250

µA

LEA,

LEA, LEB, LEB = –2 V

Logic Input Range

–2

+3

V

DIGITAL OUTPUTS

Logic “1” Voltage (VOH)

VCCO – 0.98

V

Q or

Q, 16.7 mA Load

Logic “0” Voltage (VOL)

VCCO – 1.5

V

Q or

Q, 10 mA Load

Slew Rate

1

V/ns

VCCO Range

0

8

V

SWITCHING PERFORMANCE

Propagation Delay

Input to Output

1.8

ns

VIN = 2 V p-p,

Latch Enable to Output

2

ns

HCOMP = 1 V, LCOMP = 1 V

Propagation Delay Temperature Coefficient

2

ps/

°C

Propagation Delay Change with Respect to

Slew Rate: 0.5 V, 1.0 V, 3.0 V/ns

<

± 100

ps

VIN = 0 V to 5 V

Slew Rate: 5.0 V/ns

<

± 350

ps

VIN = 0 V to 5 V

Amplitude: 1.0 V, 3.0 V, 5.0 V

<

± 200

ps

VIN = 1.0 V/ns

Equivalent Input Rise Time

450

ps

VIN = 0 V to 3 V, 3 V/ns

Pulsewidth Linearity

<

± 200

ps

VIN = 0 V to 3 V, 3 V/ns, PW = 3 ns–8 ns

Settling Time

25

ns

Settling to

±8 mV, VIN = 1 V to 0 V

Latch Timing

Input Pulsewidth

1.68

ns

Setup Time

1.0

ns

Hold Time

1.1

ns

Hysteresis

6

mV

Latch Inputs Programmed for Hysteresis

Specifications subject to change without notice.

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