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AD5330 Datasheet(PDF) 14 Page - Analog Devices |
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AD5330 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 20 page  REV. 0 AD5330/AD5331/AD5340/AD5341 –14– Resistor String The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. TO OUTPUT AMPLIFIER R R R R R VREF Figure 28. Resistor String DAC Reference Input There is a reference input pin for the DAC. The reference input is buffered on the AD5330/AD5340/AD5341 but can be config- ured as unbuffered also. The reference input of the AD5331 is unbuffered. The buffered/unbuffered option is controlled by the BUF pin. In buffered mode (BUF = 1), the current drawn from an external reference voltage is virtually zero as the impedance is at least 10 M Ω. The reference input range is 1 V to 5 V with a 5 V supply. In unbuffered mode (BUF = 0), the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to headroom and footroom of the reference ampli- fier. The impedance is still large at typically 180 k Ω for 0–V REF mode and 90 k Ω for 0–2 VREF mode. If there is an external buffered reference (e.g., REF192) there is no need to use the on-chip buffer. Output Amplifier The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on VREF, GAIN, the load on VOUT, and offset error. If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 VREF. However, because of clamping, the maximum output is limited to VDD – 0.001 V. The output amplifier is capable of driving a load of 2 k Ω to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in Figure 15. The slew rate is 0.7 V/ µs with a half-scale settling time to ± 0.5 LSB (at eight bits) of 6 µs with the output unloaded. See Figure 20. PARALLEL INTERFACE The AD5330, AD5331, and AD5340 load their data as a single 8-, 10-, or 12-bit word, while the AD5341 loads data as a low byte of eight bits and a high byte containing four bits. Double-Buffered Interface The AD5330/AD5331/AD5340/AD5341 DACs all have double- buffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the input register under control of the Chip Select ( CS) and Write (WR). Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are only updated when LDAC is taken low. Double-buffering is also useful where the DAC data is loaded in two bytes, as in the AD5341, because it allows the whole data word to be assembled in parallel before updating the DAC register. This prevents spurious outputs that could occur if the DAC register were updated with only the high byte or the low byte. These parts contain an extra feature whereby the DAC regis- ter is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC register is filled with the contents of the input register. In the case of the AD5330/AD5331/ AD5340/AD5341, the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk. Clear Input ( CLR) CLR is an active low, asynchronous clear that resets the input and DAC registers. Chip Select Input ( CS) CS is an active low input that selects the device. Write Input ( WR) WR is an active low input that controls writing of data to the device. Data is latched into the input register on the rising edge of WR. Load DAC Input ( LDAC) LDAC transfers data from the input register to the DAC register (and hence updates the outputs). Use of the LDAC function enables double-buffering of the DAC data, GAIN, and BUF. There are two LDAC modes: Synchronous Mode: In this mode the DAC register is updated after new data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed as in Figure 1. Asynchronous Mode: In this mode the outputs are not updated at the same time that the input register is written to. When LDAC goes low, the DAC register is updated with the contents of the input register. High-Byte Enable Input (HBEN) High-Byte Enable is a control input on the AD5341 only that determines if data is written to the high-byte input register or the low-byte input register. |
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