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A8582KLPTR-T Datasheet(PDF) 3 Page - Allegro MicroSystems |
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A8582KLPTR-T Datasheet(HTML) 3 Page - Allegro MicroSystems |
3 / 32 page Wide Input Voltage, 2.4 MHz, 2.0 A Asynchronous Buck Regulator A8582 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Functional Block Diagram FSET VREF 0.8 V VREF tOFF(MIN) 70 mΩ 10 Ω 90%×VREF 85%×VREF Current Sense Amp OCP VREG POR VREG BS UVLO FBOK BOOT – SW VSS – 400 mV PWM Comp Adj Adj Reset DOM PWM Ramp Offset 300 mV PWM Clk fSW SYNC Regulator EN FBOK Sleep EN/SYNC Comp Error Amp OVP Comp EN/SYNC >1.2 × fSW VIN VIN VIN FBX FB 150 nA 10 μA 20 μA POK SW BOOT SW OSC 3.5 kΩ 0.85 V Typ 1.25 V Typ 1.65 V Typ 2.9 V + – + – + + – OVP S R Q Q Slope Compensation EN/SYNC SS GND PAD GND FAULT = 1, if: EN = 0, or UVLO = 1, or OVP = 1, or Diode Missing = 1 HICCUP = 1, if Hiccup protection enabled (VFB < 625 mV) and a net count of > 7 OCP events occur 1500 Ω 125 ns COMP ∑ UVLO (VIN) Diode Missing HICCUP Latched Hiccup Protection Hiccup reset VSS = 235 mV Typ Clamp 1.7 V Typ 40 kΩ Typ Rising Digital OFF OFF TSD POR FAULT Fault Logic UVLO (VIN) OCP Latch reset EN/SYNC toggle OVP Diode Missing A A B B 114%×VREF |
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