Full-Bridge DMOS PWM Motor Drivers

A4952 and

A4953

9

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package LJ, 8-Pin SOICN

with exposed thermal pad

3.30

2

1

8

Reference land pattern layout (reference IPC7351

SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a multilayer

PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

C

1.27

5.60

2.41

1.75

0.65

2.41 NOM

3.30 NOM

C

SEATING

PLANE

1.27 BSC

GAUGE PLANE

SEATING PLANE

A Terminal #1 mark area

B

C

B

2

1

8

C

SEATING

PLANE

C

0.10

8X

0.25 BSC

1.04 REF

1.70 MAX

For Reference Only; not for tooling use (reference MS-012BA)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

4.90 ±0.10

3.90 ±0.10

6.00 ±0.20

0.51

0.31

0.15

0.00

0.25

0.17

1.27

0.40

8°

0°

Exposed thermal pad (bottom surface); dimensions may vary with device

A

Branded Face