REV. 0

AD5302/AD5312/AD5322

–5–

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

1

LDAC

Active low control input that transfers the contents of the input registers to their respective DAC regis-

ters. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new

data. This allows simultaneous update of both DAC outputs

Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be de-

coupled to GND.

Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or

an unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range

Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or

an unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range from

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

7

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in

on the falling edges of the following 16 clocks. If

SYNC is taken high before the 16th falling edge, the

rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the device.

8

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock in-

put. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each

write cycle.

9

DIN

Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the

falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

10

GND

Ground reference point for all circuitry on the part.

TERMINOLOGY

RELATIVE ACCURACY

For the DAC, relative accuracy or Integral Nonlinearity (INL)

is a measure of the maximum deviation, in LSBs, from a straight

line passing through the actual endpoints of the DAC transfer

function. A typical INL vs. code plot can be seen in Figure 4.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of

±1 LSB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. A typical DNL vs. code plot can be seen

in Figure 7.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output

amplifier. It is expressed as a percentage of the full-scale range.

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia-

tion in slope of the actual DAC transfer characteristic from the

ideal expressed as a percentage of the full-scale range.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes in

temperature. It is expressed in (ppm of full-scale range)/

°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in tem-

perature. It is expressed in (ppm of full-scale range)/

°C.

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the impulse

injected into the analog output when the code in the DAC regis-

ter changes state. It is normally specified as the area of the glitch

in nV-secs and is measured when the digital code is changed by

1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or

100 . . . 00 to 011 . . . 11).

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected into the

analog output of the DAC from the digital input pins of the

device, but is measured when the DAC is not being written to

(

SYNC held high). It is specified in nV-secs and is measured

with a full-scale change on the digital input pins, i.e., from all 0s

to all 1s and vice versa.

ANALOG CROSSTALK

This is the glitch impulse transferred to the output of one DAC

due to a change in the output of the other DAC. It is measured

by loading one of the input registers with a full-scale code change

(all 0s to all 1s and vice versa) while keeping

LDAC high. Then

pulse

LDAC low and monitor the output of the DAC whose

digital code was not changed. The area of the glitch is expressed

in nV-secs.