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ACT8828 Datasheet(PDF) 6 Page - Active-Semi, Inc |
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ACT8828 Datasheet(HTML) 6 Page - Active-Semi, Inc |
6 / 50 page ACT8828 Rev 7, 15-Nov-12 Innovative Power TM - 6 - www.active-semi.com Copyright © 2012 Active-Semi, Inc. ActivePMU TM and ActivePathTM are trademarks of Active-Semi. I 2CTM is a trademark of NXP. PIN DESCRIPTIONS CONT’D PIN NAME DESCRIPTION 24 nPBIN Master Enable Input. Drive nPBIN to GA through a 100kΩ resistor to enable the IC, drive nPBIN directly to GA to assert a Hard-Reset condition. Refer to the System Startup & Shutdown section for more information. nPBIN is internally pulled up to VSYS through a 50kΩ resistor. 25 OUT3 Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 26 GP3 Power Ground for REG3. Connect GA, GP1, GP2, GP3, and GP4 together at a single point as close to the IC as possible. 27 SW3 Switching Node Output for REG3. Connect this pin to the switching end of the inductor. 28 VP3 Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as possible to the IC. 29 FB4 Feedback Sense for REG4. Connect this pin to the LED string current sense resistor to sense the LED current. 30 OVP4 Over-Voltage Protection Input for REG4. Connect this pin to the output node through a 10kΩ resistor to sense and prevent over-voltage conditions. 31 GP4 Power Ground for REG4. Connect GP4 directly to a power ground plane. Connect GA, GP1, GP2, GP3, and GP4 together at a single point as close to the IC as possible. 32 SW4 Switching Node Output for REG4. Connect this pin to the switching end of the inductor. 33 nSTAT Active-Low Open-Drain Charger Status Output. nSTAT has a 5mA (typ) current limit, allowing it to directly drive an indicator LED without additional external components. To generate a logic-level output, connect nSTAT to an appropriate supply voltage (typically VSYS) through a 10kΩ or greater pull-up resistor. See the Charge Status Indication section for more information. 34 ON2 Independent Enable Control Input for REG2. Drive ON2 to a logic high for normal operation, drive to GA or a logic low to disable REG2. Do not leave ON2 floating. 35 GA Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1, GP2, GP3, and GP4 together at a single point as close to the IC as possible. 36 REFBP Reference Noise Bypass. Connect a 0.01µF ceramic capacitor from REFBP to GA. This pin is discharged to GA in shutdown. 37 ON4 Independent Enable Control Input for REG4. Drive ON4 to a logic high for normal operation, drive to GA or a logic low to disable REG4. Do not leave ON4 floating. 38 nRSTO Open-Drain Reset Output. nRSTO asserts low whenever REG1 is out of regulation, and remains low for 260ms (typ) after REG1 reaches regulation. 39 nIRQ Open-Drain Interrupt Output. nIRQ asserts any time nPBIN is asserted or an unmasked fault condition exists. When asserted by nPBIN, nIRQ automatically de-asserts when nPBIN is released. When asserted by an unmasked fault condition, nIRQ remains asserted until the ACT8828 is polled by the microprocessor. See the nIRQ Output section for more information. 40 CHGLEV Charging State Select Input. When ACIN = 0 charge current is internally set; Drive CHGLEV to a logic-high for high-current USB charging mode (maximum charge current is 500mA), drive CHGLEV to a logic-low for low- current USB charging mode (maximum charge current is 100mA). When ACIN = 1 charge current is externally set by RISET; Drive CHGLEV to a logic-high to for high -current charging mode (ISET (mA) = KISET × 1V/(RISET (kΩ) +0.031) where KISET = 628), drive CHGLEV to a logic-low for low-current charging mode (ISET (mA) = KISET × 1V/(RISET (kΩ) + 31) where KISET = 314). Do not leave CHGLEV floating. EP EP Exposed Pad. Must be soldered to ground on the PCB. |
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