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AD5203AR10 Datasheet(PDF) 3 Page - Analog Devices |
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AD5203AR10 Datasheet(HTML) 3 Page - Analog Devices |
3 / 12 page –3– REV. 0 AD5203 NOTES 1Typicals represent average readings at +25 °C and V DD = +5 V. 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I W = VDD/R for both VDD = +3 V or VDD = +5 V. 3V AB = VDD, Wiper (VW) = No connect. 4INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit. 5Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode. 8Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I DD vs. logic voltage inputs result in minimum power dissipation. 9P DISS is calculated from (IDD × V DD). CMOS logic level inputs result in minimum power dissipation. 10All dynamic characteristics use V DD = +5 V. 11Measured at a V W pin where an adjacent VW pin is making a full-scale voltage change. 12See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V. Input logic should have a 1 V/ µs minimum slew rate. 13Propagation delay depends on value of V DD, RL and CL. See Operation section. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD IAB, IAW, IBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V Operating Temperature Range . . . . . . . . . . . –40 °C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150 °C Storage Temperature . . . . . . . . . . . . . . . . . . –65 °C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300 °C Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/ θ JA Thermal Resistance θ JA P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 °C/W SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 °C/W TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 °C/W *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table I. Serial-Data Word Format ADDR DATA B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB 27 26 25 20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5203 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE SDI CLK CS VOUT 1 0 1 0 1 0 VDD 0V D0 D1 D2 D3 D4 D5 A0 A1 DAC REGISTER LOAD Figure 1a. Timing Diagram CLK VOUT 1 0 1 0 1 0 VDD 0V SDI (DATA IN) SDO (DATA OUT) CS 1 0 Ax OR Dx Ax OR Dx A'x OR D'x tDS tDH tPD MAX tPD MIN tCH tCS1 tCL tCSS tCSH 1 LSB 1 LSB ERROR BAND tCSW tS A'x OR D'x Figure 1b. Detail Timing Diagram VOUT VDD 0V RS 1 0 1 LSB 1 LSB ERROR BAND tS tRS Figure 1c. Reset Timing Diagram |
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