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AD421BN Datasheet(PDF) 3 Page - Analog Devices |
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AD421BN Datasheet(HTML) 3 Page - Analog Devices |
3 / 14 page AD421 –3– REV. C TIMING CHARACTERISTICS1, 2, 3 Parameter (B Versions) Units Conditions/Comments tCK 100 ns min Data Clock Period tCL 50 ns min Data Clock Low Time tCH 50 ns min Data Clock High Time tDW 30 ns min Data Stable Width tDS 30 ns min Data Setup Time tDH 0 ns min Data Hold Time tLD 50 ns min Latch Delay Time tLL 50 ns min Latch Low Time tLH 50 ns min Latch High Time NOTES 1Guaranteed by characterization at initial product release, not production tested. 2See Figures 1 and 2. 3All input signals are specified with tr = tf = 5 ns (10% to 90% of V CC ) and timed from a voltage level of (VIN + VIL )/2; tr and tf should not exceed 1 µs on any digital input. Specifications subject to change without notice. WORD "N" WORD "N +1" 10 1 1 1 1 11 1 1 00 0 0 0 0 1 0 0 1 CLOCK DATA LATCH Figure 1. Serial Interface Waveforms (Normal Data Load) CLOCK DATA LATCH t CK t CL t CH t DS t DH t DW t LD t LL t LH Figure 2. Serial Interface Timing Diagram (VCC = +3 V to +5 V, TA = TMIN to TMAX unless otherwise noted) |
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