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AD2S82AHP Datasheet(PDF) 10 Page - Analog Devices

Part # AD2S82AHP
Description  Variable Resolution, Monolithic Resolver-to-Digital Converters
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD2S82AHP Datasheet(HTML) 10 Page - Analog Devices

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REV. B
–10–
AD2S81A/AD2S82A
BUSY
RIPPLE
CLK
DATA
DIR
DATA
BYTE
SELECT
DATA
ENABLE
INHIBIT
VL
VH
t1
VH
t2
t4
VH
VL
VH
VH
t3
t5
VL
VH
INHIBIT
t6
VH
t7
t8
t9
VL
VL
VL
t10
VZ
VH
VL
t11
VL
VH
VH
VL
t13
t12
PARAMETER
TMIN
TMAX
CONDITION
t1
200
600
BUSY WIDTH VH–VH
t2
10
25
RIPPLE CLOCK VH TO BUSY VH
t3
470
580
RIPPLE CLOCK VL TO NEXT BUSY VH
t4
16
45
BUSY VH TO DATA VH
t5
3
25
BUSY VH TO DATA VL
t6
70
140
INHIBIT VH TO BUSY VH
t7
485
625
MIN DIR VH TO BUSY VH
t8
515
670
MIN DIR VH TO BUSY VH
t9
600
INHIBIT VL TO DATA STABLE
t10
40
110
ENABLE VL TO DATA VH
t11
35
110
ENABLE VL TO DATA VL
t12
60
140
BYTE SELECT VL TO DATA STABLE
t13
60
125
BYTE SELECT VH TO DATA STABLE
Figure 3. Digital Timing
PHASE-
SENSITIVE
DEMODULATOR
AC ERROR
RATIO
MULTIPLIER
A1 sin ( –
) sin
t
sin
sin
t
cos
sin
t
DIGITAL
VCO
C4
C5
R5
R4
R6
VELOCITY
CLOCK
DIRECTION
INTEGRATOR
Figure 4. AD2S81A/AD2S82A Functional Diagram
CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE
The AD2S81A/AD2S82A allows the user greater flexibility in
choosing the dynamic characteristics of the resolver-to-digital
conversion to ensure the optimum system performance. The
characteristics are set by the external components shown in
Figure 1, and the Component Selection section explains how to
select desired maximum tracking rate and bandwidth values.
The following paragraphs explain in greater detail the circuit of
the AD2S81A/AD2S82A and the variations in the dynamic
performance available to the user.
Loop Compensation
The AD2S81A and AD2S82A (connected as shown in Figure
1a and 1b) operates as a type 2 tracking servo loop where the
VCO/counter combination and integrator perform the two inte-
gration functions inherent in a type 2 loop.
Additional compensation in the form of a pole/zero pair is re-
quired to stabilize any type 2 loop to avoid the loop gain charac-
teristic crossing the 0 dB axis with 180
° of additional phase lag,
as shown in Figure 6. This compensation is implemented by the
integrator components (R4, C4, R5, C5).
The overall response of such a system is that of a unity gain
second order low pass filter, with the angle of the resolver as the
input and the digital position data as the output.
The AD2S81A/AD2S82A does not have to be connected as
tracking converter, parts of the circuit can be used indepen-
dently. This is particularly true of the Ratio Multiplier which
can be used as a control transformer (see Application Note).
A block diagram of the AD2S81A/AD2S82A is given in
Figure 4.


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