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AD22151 Datasheet(PDF) 4 Page - Analog Devices |
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AD22151 Datasheet(HTML) 4 Page - Analog Devices |
4 / 8 page AD22151 –4– REV. 0 FIELD – Gauss 0.025 0.020 0 0.015 0.005 0.010 –600 –400 –200 0 200 400 600 Figure 5. Signal Drift Over Temperature (–40 °C to +150°C) vs. Field (–200 ppm); +5 V Supply TEMPERATURE – C 0.25 0.20 0 0.15 0.05 0.10 –40 10 60 110 160 –0.05 Figure 6. Gain Variation from +25 °C vs. Temperature (–200 ppm) Field; R1 –15 k Ω FIELD – Gauss 0.045 0.040 0 0.035 0.025 0.030 –800 –400 –200 0 200 400 600 0.020 0.015 0.010 0.005 –600 800 Figure 7. Signal Drift Over Temperature (–40 °C to +150°C) vs. Field (–2000 ppm); +5 V Supply TEMPERATURE – C 2.0 1.8 1.0 1.6 1.2 1.4 –40 10 60 110 160 –0.2 0.8 0.6 0.4 0.2 0 Figure 8. Gain Variation (from +25 °C) vs. Temperature (–2000 ppm Field; R1 = 12 k Ω) TEMPERATURE COMPENSATION The AD22151 incorporates a “thermistor” transducer that detects relative chip temperature within the package. This function provides a compensation mechanism for the various temperature dependencies of the Hall cell and magnet combina- tions. The temperature information is accessible at Pins 1 and 2 ( ≈ +2900 ppm /°C) and Pin 3 (≈ –2900 ppm/°C) as represented by Figure 9. The compensation voltages are trimmed to con- verge at VCC/2 at +25°C. Pin 3 is internally connected to the negative TC voltage via an internal resistor (see Functional Block Diagram). An external resistor connected between Pin 3 and Pins 1 or 2 will produce a potential division of the two comple- mentary TC voltages to provide optimal compensation. The aforementioned Pin 3 internal resistor provides a secondary TC designed to reduce second order Hall cell temperature sensitivity. TEMPERATURE – C 1.0 0.8 0 0.6 0.2 0.4 150 112 74 –2 –40 –0.2 –0.4 –0.6 –0.8 –1.0 36 TC1, TC2 VOLTS TC3 VOLTS Figure 9. TC1, TC2 and TC3 with Respect to Reference vs. Temperature The voltages present at Pins 1, 2 and 3 are proportional to the supply voltage. The presence of the Pin 2 internal resistor distinguishes the effective compensation ranges of Pins 1 and 2 (see temperature configuration in Figures 1 and 2, and typical resistor values in Figures 10 and 11). Variation occurs in the operation of the gain temperature compensation for two reasons. First, the die temperature within |
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