REV. 0

AD1959

–7–

POWER SUPPLY AND VOLTAGE REFERENCE

The AD1959 is designed for five-volt supplies. Separate power

supply pins are provided for the analog, digital, and PLL sec-

tions. These pins should be bypassed with 100 nF ceramic chip

capacitors, as close to the pins as possible, to minimize noise. A

bulk aluminum electrolytic capacitor of at least 22

µF should

also be provided on the same PC board. For best performance it

is recommended that the analog supply be separate from the

digital and PLL supply. It is recommended that all supplies be

isolated by ferrite beads in series with each supply. It is expected

that the digital and PLL sections will be run from a common

supply but isolated from one another. It is important that the

analog supply be as clean as possible.

The internal voltage reference is brought out on Pin 21 (FILTR)

and should be bypassed as close as possible to the chip with a

parallel combination of 10

µF and 100 nF The reference voltage

may be used to bias external op amps to the common-mode

voltage of the analog output signal pins. The current drawn

µA.

SERIAL DATA PORTS – DATA FORMAT

The DAC serial data input mode defaults to I

Bits 4 and 5 in the DAC control register, the mode can be

changed to RJ, DSP, or LJ. The word width defaults to 24 bits

but can be changed by programming Bits 8 and 9 in the DAC

Control Register.

Figure 2 shows the serial mode formats.

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

MSB

MSB

MSB

MSB

MSB

MSB

MSB

LSB

LSB

LSB

LSB

LSB

LSB

LSB

LSB

LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL

RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL

DSP MODE – 16 TO 24 BITS PER CHANNEL

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL.

3. BCLK FREQUENCY IS NORMALLY 64

LRCLK BUT MAY BE OPERATED IN BURST MODE.

Figure 2. Stereo Serial Modes