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CBTL04082A Datasheet(PDF) 10 Page - NXP Semiconductors |
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CBTL04082A Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 19 page CBTL04082A_CBTL04082B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 28 February 2011 10 of 18 NXP Semiconductors CBTL04082A; CBTL04082B 3.3 V, 4 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2 13. Test information CL = load capacitance; includes jig and probe capacitance. RT = termination resistance; should be equal to Zo of the pulse generator. All input pulses are supplied by generators having the following characteristics: PRR ≤ 5MHz; Zo =50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns. Fig 5. Test circuitry for switching times Fig 6. Test circuit Table 9. Test data Test Load Switch CL RL tPLZ, tPZL (output on B side) 50 pF 200 Ω 2 × VIC tPHZ, tPZH (output on B side) 50 pF 200 Ω GND tPD -200 Ω open PULSE GENERATOR VO CL 50 pF RL 200 Ω 002aag014 RT VIC VDD DUT RL 200 Ω 2 × VIC open GND 002aae655 4-PORT, 20 GHz NETWORK ANALYZER PORT 1 PORT 4 DUT PORT 2 PORT 3 |
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