LE24LB642CS

3) Notes on write protect operation

This product prohibits all 64k bit writing when the WP pin is high. To ensure full write protection, the WP is set high

for all periods from the start condition to the stop condition, and the conditions below must be satisfied.

VDD=1.7 to 3.6V

Item

Symbol

min

typ

max

unit

WP Setup time

tSU.WP

600

ns

WP Hold time

tHD.WP

600

ns

SCL

SDA

tSU.WP

tHD.WP

WP

Start condition

Stop condition

4) Precautions when turning on the power

This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is

turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data

guarantees are given in the event of an instantaneous power failure during the internal write operation.

VDD=1.7 to 3.6V

Item

Symbol

min

typ

max

unit

Power rise time

tRISE

100

ms

Power off time

tOFF

10

ms

Power bottom voltage

Vbot

0.2

V

VDD

0V

tOFF

tRISE

Vbot

Notes:

1) The SDA pin must be set to high and the SCL pin to low or high.

2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state.

A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise

After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high.

VDD

SCL

SDA

tLOW

tDH

tSU.DAT

VDD

SCL

SDA

tSU.DAT

No.A1464-10/11