Electronic Components Datasheet Search
Selected language     English  ▼
Part Name
         Description


AD1852JRS Datasheet(PDF) 8 Page - Analog Devices

Part No. AD1852JRS
Description  Stereo, 24-Bit, 192 kHz Multibit DAC
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

 8 page
background image
AD1852
–8–
REV. 0
Note that the AD1852 is capable of a 32
× F
S BCLK frequency
“packed mode” where the MSB is left-justified to an L/
RCLK
transition, and the LSB is right-justified to the opposite L/
RCLK
transition. L/
RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 5.
Master Clock Autodivide Feature
The AD1852 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter-
nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above. Master clock should be synchronized with L/
RCLK but
phase relation between master clock and L/
RCLK is not critical.
D15
D14
D0
tCHD
tCCH
tCSU
tCCL
tCLL
tCLH
CDATA
CCLK
CLATCH
tCLSU
Figure 7. Serial Control Port Timing
Table II.
Nominal Input
Internal Sigma-
Chip Mode
Allowable Master Clock Frequencies
Sample Rate
Delta Clock Rate
INT8
× Mode
256
× F
S, 384
× F
S, 512
× F
S, 768
× F
S, 1024
× F
S
48 kHz
128
× F
S
INT4
× Mode
128
× F
S, 192
× F
S, 256
× F
S, 384
× F
S, 512
× F
S
96 kHz
64
× F
S
INT2
× Mode
64
× F
S, 96
× F
S, 128
× F
S, 192
× F
S, 256
× F
S
192 kHz
32
× F
S
SPI REGISTER DEFINITIONS
The SPI port allows flexible control of many chip parameters. It is
organized around three registers; a LEFT-CHANNEL VOLUME
register, a RIGHT-CHANNEL VOLUME register, and a
CONTROL register. Each WRITE operation to the AD1852
SPI control port requires 16 bits of serial data in MSB-first format.
The bottom two bits are used to select one of three registers,
and the top 14 bits are then written to that register. This allows
a write to one of the three registers in a single 16-bit transaction.
The SPI CCLK signal is used to clock in the data. The incom-
ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise
to clock the data internally into the AD1852.




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download



Related Electronics Part Number

Part NumberComponents DescriptionHtml ViewManufacturer
AD1853Stereo 24-Bit 192 kHz Multibit DAC 1 2 3 4 5 MoreAnalog Devices
CS4391A24-BIT 192 kHz STEREO DAC WITH VOLUME CONTROL 1 2 3 4 5 MoreCirrus Logic
CS4340A24-Bit 192 kHz Stereo DAC for Audio  1 2 3 4 5 MoreCirrus Logic
CS4341A24-Bit 192 kHz Stereo DAC with Volume Control  1 2 3 4 5 MoreCirrus Logic
CS439124-Bit 192 kHz Stereo DAC with Volume Control  1 2 3 4 5 MoreCirrus Logic
CS439224-Bit 192 kHz Stereo DAC with Volume Control  1 2 3 4 5 MoreCirrus Logic
AD1833A24-Bit 192 kHz DAC 1 2 3 4 5 MoreAnalog Devices
CS427224-Bit 192 kHz Stereo Audio CODEC 1 2 3 4 5 MoreCirrus Logic
AD19394 ADC/8 DAC with PLL 192 kHz 24-Bit CODEC 1 2 3 4 5 MoreAnalog Devices
AD1833Multichannel 24-Bit 192 kHz DAC 1 2 3 4 5 MoreAnalog Devices

Link URL

Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com 2003 - 2017    


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl