AD14160 datasheet(28/52 Pages) AD

Part #	AD14160

Description	Quad-SHARC DSP Multiprocessor Family

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AD14160/AD14160L

–28–

REV. A

transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK

(not

DMAG). For Paced Master mode, the “Memory Read–Bus

Master”, “Memory Write–Bus Master”, and “Synchronous

Read/Write–Bus Master” timing specifications for ADDR31-0,

RD, WR, MS

3-0, SW, PAGE, DATA47-0, and ACK also apply.

40 MHz–5 V

40 MHz–3.3 V

Parameter

Min

Max

Min

Max

Units

Timing Requirements:

tSDRLC

DMARx Low Setup Before CLKIN1

5.5

ns

tSDRHC

DMARx High Setup Before CLKIN1

5.5

ns

tWDR

DMARx Width Low (Nonsynchronous)

6

ns

tSDATDGL

Data Setup After

DMAGx Low2

9 + 5DT/8

ns

tHDATIDG

Data Hold After

DMAGx High

2.5

ns

tDATDRH

Data Valid After

DMAGx High2

15 + 7DT/8

ns

tDMARLL

DMAGx Low Edge to Low Edge

23 + 7DT/8

ns

tDMARH

DMAGx Width High

6

ns

Switching Characteristics:

tDDGL

DMAGx Low Delay After CLKIN

9 + DT/4

16 + DT/4

9 + DT/4

16 + DT/4

ns

tWDGH

DMAGx High Width

6 + 3DT/8

ns

tWDGL

DMAGx Low Width

12 + 5DT/8

ns

tHDGC

DMAGx High Delay After CLKIN

–2 – DT/8

7 – DT/8

–2 – DT/8

7 – DT/8

ns

tVDATDGH

Data Valid Before

DMAGx High3

7 + 9DT/16

ns

tDATRDGH

Data Disable After

DMAGx High4

–0.5

8

–0.5

8

ns

tDGWRF

WR Low Before DMAGx Low

–0.5

2.5

–0.5

2.5

ns

tDGWRH

DMAGx Low Before WR High

9.5 + 5DT/8 + W

ns

tDGWRR

WR High Before DMAGx High

0.5 + DT/16

3.5 + DT/16

0.5 + DT/16

3.5 + DT/16

ns

tDGRDF

RD Low Before DMAGx Low

–0.5

2.5

–0.5

2.5

ns

tDRDGH

RD Low Before DMAGx High

10.5 + 9DT/16 + W

ns

tDGRDR

RD High Before DMAGx High

–0.5

3.5

–0.5

3.5

ns

tDGWR

DMAGx High to WR, RD, DMAGx Low

5 + 3DT/8 + HI

ns

tDADGH

Address/Select Valid to

DMAGx High

16 + DT

ns

tDDGHA

Address/Select Hold After

DMAGx High

–1.5

ns

W = (number of wait states specified in WAIT register)

× t

CK.

HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

NOTES

1Only required for recognition in the current cycle.

2t

SDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the

data can be driven tDATDRH after DMARx is brought high.

3t

VDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH = 7 + 9DT/16 + (n × tCK) where

n equals the number of extra cycles that the access is prolonged.

4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

DMA Handshake

These specifications describe the three DMA handshake modes.

In all three modes

DMAR is used to initiate transfers. For hand-

shake mode,

DMAG controls the latching or enabling of data

externally. For external handshake mode, the data transfer is

controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0,

ACK, and

DMAG signals. For Paced Master mode, the data

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