W981216AH datasheet(9/44 Pages) WINBOND

Part #	W981216AH

Description	2M x 16 bit x 4 Banks SDRAM

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Manufacturer	WINBOND [Winbond]

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W981216AH

2M x 16 bit x 4 Banks SDRAM

Revision 1.0

Publication Release Date: March, 1999

- 9 -

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth

table for the operation commands.

Table 1 Truth Table

( note (1) , (2) )

command

Device state

CKEn-1

CKEn

DQM

BS0,1

A10

A11,

A9-0

CS

RA

CAS

WE

Bank Active

Idle

H

x

v

L

H

Bank Precharge

Any

H

x

v

L

x

L

H

L

Precharge All

Any

H

x

H

x

L

H

L

Write

Active (3)

H

x

v

L

v

L

H

L

Write with Autoprecharge

Active (3)

H

x

v

H

v

L

H

L

Read

Active (3)

H

x

v

L

v

L

H

L

H

Read with Autoprecharge

Active (3)

H

x

v

H

v

L

H

L

H

Mode Register Set

Idle

H

x

v

L

No - Operation

Any

H

x

L

H

Burst Stop

Active (4)

H

x

L

H

L

Device Deselect

Any

H

x

H

x

Auto - Refresh

Idle

H

x

L

H

Self - Refresh Entry

Idle

H

L

x

L

H

Self Refresh Exit

idle

(S.R.)

L

H

x

H

L

x

H

x

H

x

Clock suspend Mode Entry

Active

H

L

x

Power Down Mode Entry

Idle

Active (5)

H

L

x

H

L

x

H

x

H

x

Clock Suspend Mode Exit

Active

L

H

x

Power Down Mode Exit

Any

(power down)

L

H

x

H

L

x

H

x

H

x

Data write/Output Enable

Active

H

x

L

x

Data Write/Output Disable

Active

H

x

H

x

Notes: (1) v= valid x = Don't care L= Low Level H= High Level

(2) CKEn signal is input level when commands are provided.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

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