W981208AH datasheet(3/44 Pages) WINBOND

Part #	W981208AH

Description	4M x 8 bit x 4 Banks SDRAM

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Manufacturer	WINBOND [Winbond]

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W981208AH

4M x 8 bit x 4 Banks SDRAM

Revision 1.0

Publication Release Date: March, 1999

- 3 -

Pin Assignment

Pin Number

Pin Name

Function

Description

23 ~ 26, 22,

29 ~35

A0~ A11

Address

Multiplexed pins for row and column address.

Row address : A0 ~ A11. Column address: A0 ~ A9.

20, 21

BS0, BS1

Bank Select

Select bank to activate during row address latch time, or bank

to read/write during address latch time.

2, 5, 8, 11,

44, 47, 50, 53

DQ0 ~ DQ7

Data Input/

Output

Multiplexed pins for data output and input.

19

CS#

Chip Select

Disable or enable the command decoder. When command

decoder is disabled, new command is ignored and previous

operation continues.

18

RAS#

Row Address

Strobe

Command input. When sampled at the rising edge of the clock,

RAS#, CAS# and WE# define the operation to be executed.

17

CAS#

Column Address

Strobe

Referred to RAS#

16

WE#

Write Enable

Referred to RAS#

39

DQM

input/output mask

The output buffer is placed at Hi-Z(with latency of 2) when DQM

is sampled high in read cycle. In write cycle, sampling DQM

high will block the write operation with zero latency.

38

CLK

Clock Inputs

System clock used to sample inputs on the rising edge of clock.

37

CKE

Clock Enable

CKE controls the clock activation and deactivation. When CKE

is low, Power Down mode, Suspend mode, or Self Refresh

mode is entered.

1, 14, 27

VCC

Power ( +3.3 V )

Power for input buffers and logic circuit inside DRAM.

28, 41, 54

VSS

Ground

Ground for input buffers and logic circuit inside DRAM.

3, 9, 43, 49

VCCQ

Power ( + 3.3 V )

for I/O buffer

Separated power from VCC, used for output buffers to improve

noise.

6, 12, 46, 52

VSSQ

Ground for I/O

buffer

Separated ground from VSS, used for output buffers to improve

noise.

4, 7, 10, 13,

15, 36, 40, 42,

45, 48, 51

NC

No Connection

No connection

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